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- Abdulaziz, Mohammed, 1983, et al.
(författare)
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A 10-mW mm-wave phase-locked loop with improved lock time in 28-nm FD-SOI CMOS
- 2019
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Ingår i: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480 .- 1557-9670. ; 67:4, s. 1588-1600
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Tidskriftsartikel (refereegranskat)abstract
- © 2019 IEEE. This paper presents a millimeter-wave (mm-wave) phase-locked loop (PLL), with an output frequency centered at 54.65 GHz. It demonstrates a mode-switching architecture that considerably improves the lock time, by seamlessly switching between a low-noise mode and a fast-locking mode that is only used during settling. The improvement is used to counteract the increased lock-time caused by cycle-slips that results from using a high reference frequency of 2280 MHz, which is several hundred times the loop bandwidth. Such a reference frequency alleviates the noise requirements on the PLL and is readily available in 5G systems, from the radio frequency PLL. The mm-wave PLL is implemented in a low-power 28-nm fully depleted silicon-on-insulator CMOS process, and its active area is just 0.19 mm 2 . The PLL also features a novel double injection-locked divide-by-3 circuit and a charge-pump mismatch compensation scheme, resulting in state-of-the-art power consumption, and jitter performance in the low-noise mode. In this mode, the in-band phase noise is between-93 and-96 dBc/Hz across the tuning range, and the integrated jitter is between 176 and 212 fs. The total power consumption of the mm-wave PLL is only 10.1 mW, resulting in a best-case PLL figure-of-merit (FOM) of-245 dB. The lock time in low-noise mode is up to 12μs, which is improved to 3μs by switching to the fast-locking mode, at the temporary expense of a power consumption increase to 15.1 mW, an integrated jitter increase to between 245 and 433 fs, and an FOM increase to between-235 and-240 dB.
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| 2. |
- Abdulaziz, Mohammed, 1983, et al.
(författare)
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Improvement of AM-PM in a 33-GHz CMOS SOI Power Amplifier Using pMOS Neutralization
- 2019
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Ingår i: IEEE Microwave and Wireless Components Letters. - 1558-1764 .- 1531-1309. ; 29:12, s. 798-801
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Tidskriftsartikel (refereegranskat)abstract
- This letter presents two highly efficient two-stage power amplifiers (PAs) for 5G applications, implemented in a 22-nm slilicon on insulator (SOI) CMOS technology. High efficiency is achieved by carefully designing the power cells and optimizing the layout. Capacitive neutralization is used to improve the stability and the gain. Both PAs are similar except for the use of nMOS neutralization capacitors in the first one. In the second PA, we propose the use of pMOS capacitors instead to enhance significantly both stability and AM-PM linearity at the same time. For both PAs, the saturated output power is 12.7 dBm andP1 dB is 11.9 dBm from a 0.9-V supply at 33 GHz with a power-added efficiency (PAE) at P1 dB of more than 36%. The PAE at Psat is 38% and 40% for the PA with nMOS and pMOS neutralizations, respectively. The AM-PM up to P3 dB for the PA with nMOS neutralization is 7, and for the one with pMOS neutralization, it is less than 1.3 thanks to the proposed technique.
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