| 1. |
- Shah, Zeb, et al.
(författare)
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Impact of Indoor Multipath Channels on Timing Advance for URLLC in Industrial IoT
- 2020
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Ingår i: 2020 IEEE International Conference on Communications Workshops (ICC Workshops). - : IEEE. - 9781728174402
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Konferensbidrag (refereegranskat)abstract
- In 5G radio access networks, emerging machine type communication in industrial automation, smart grids, automotives, and other applications has increased the importance of establishing accurate time reference up to the device level. For instance, executing real-time isochronous operations in collaborating robots, monitoring, and fault localization in smart grids require ultra-tight synchronization among the devices. To establish time synchronization, however, the time dissemination procedure must accurately estimate and compensate for the base station (BS) to user equipment (UE) propagation delays. In this paper, we use the timing advance (TA) mechanism as an estimator for the time of arrival (TOA) for adjusting the effects of propagation delay in synchronization procedures. We study the impact of TA binning on TOA estimation, and analyze how multipath channels deteriorate the estimation accuracy. Our analysis shows that multipath channels could introduce large errors in TOA, however, averaging the multiple consecutive TA values, in static device deployments, can bring the errors to an acceptable level, i.e., less than 1 microsecond.
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| 2. |
- Aamir, Syed Ahmed, 1980-, et al.
(författare)
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A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-nm CMOS
- 2010
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Ingår i: Proceedings of the 17th IEEE International Conference on Electronics, Circuits, and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 29-32
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Konferensbidrag (refereegranskat)abstract
- In this work, we describe the implementation of a 1. 2-V pseudo-differential operational transconductance amplifier (OTA) with common-mode feedforward (CMFF) and inherent common-mode feedback (CMFB) in a 65-nm, digital CMOS process. The OTA architecture provides an inherent CMFB when cascaded OTA structures are utilized andthis work has studied a cascaded amplifier consisting of fourstages. Due to the low-gain using core 65-nm circuit devices, the overall gain must be distributed on all four stages to acquire a gain of more than 60 dB, while maintaining a-3-dB bandwidth of 200 MHz. To achieve high gain, we propose using a modified, positive-feedback, cross-coupled input differential stage. The modified OTA achieves a high output swing of ± 0.85 V due to only two stacked transistors, 88 dB DC gain and a third-order harmonic of -60 dB for 800 mVpp at 30 MHz. Further on, in a capacitive buffer configuration, we achieve a high slew rate of 1240 V/µS, -3-dB bandwidth of 509 MHz, signal-to-noise ratio of 63 dB while consuming 10.4 mW power.
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| 3. |
- Aamir, Syed Ahmed, 1980-, et al.
(författare)
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A 500-MHz low-voltage programmable gain amplifier for HD video in 65-nm CMOS
- 2010
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Ingår i: Proceedings of 28th IEEE Norchip Conference., NORCHIP'10. - Tampere : www.ieee.org. - 9781424489718 - 9781424489725 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process. The “pseudo” switched-capacitor (SC) PGA architecture buffers the video signal, without switching, during the active video. The SC circuitry is used for setup of DC operating point during horizontal and vertical blanking periods. Additionally, it compensates for the `sync-tip' of analog video signals to an equal blanking level for increased dynamic range to the digitizer following the PGA. The operational transconductance amplifier (OTA) employed as main amplifier in the PGA is a pseudo-differential, positive-feedback input stage architecture with a common-mode feedforward (CMFF) technique. The common-mode feedback (CMFB) is provided once two OTAs are cascaded. Schematic-level simulation results show that the OTA maintains a -3-dB bandwidth of 550 MHz, while keeping the distortion HD3 at -60 dB for a 30-MHz, 850 mVpp high definition video signal. The 88 dB DC gain is distributed among four OTA stages and the overall, combined PGA achieves a signal-to-noise ratio of 63 dB. Due to only two stacked transistors, it achieves high output swing of ±0.85 V, 1240 V/μs slew rate while consuming 10.4 mW power.
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| 4. |
- Ahmed Aamir, Syed, et al.
(författare)
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1.2-V Analog Interface for a 300-MSps HD Video Digitizer in Core 65-nm CMOS
- 2014
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1063-8210 .- 1557-9999. ; 22:4, s. 888-898
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Tidskriftsartikel (refereegranskat)abstract
- This paper describes the front-end of a fully integrated analog interface for 300 MSps, high-definition video digitizers in a system on-chip environment. The analog interface is implemented in a 1.2 V, 65-nm digital CMOS process and the design minimizes the number of power domains using core transistors only. Each analog video receiver channel contains an integrated multiplexer with a current-mode dc-clamp, a programmable gain amplifier (PGA) and a pseudo second-order RC low-pass filter. The digital charge-pump clamp is integrated with low-voltage bootstrapped tee-switches inside the multiplexer, while restoring the dc component of ac-coupled inputs. The PGA contains a four-stage fully symmetric pseudo-differential amplifier with common-mode feedforward and inherent common-mode feedback, utilized in a closed loop capacitive feedback configuration. The amplifier features offset cancellation during the horizontal blanking. The video interface is evaluated using a unique test signal over a range of video formats for INL+/DNL+, INL-/DNL-. The 0.07-0.39 mV INL, 2-70 mu V DNL, and 66-74 dB of SFDR, enable us to target various formats for 9-12 bit Low-voltage digitizers.
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| 5. |
- Ahmed Aamir, Syed, et al.
(författare)
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Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers
- 2013
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Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS), 2013. - : IEEE conference proceedings. - 9781467357609 ; , s. 381-384
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Konferensbidrag (refereegranskat)abstract
- This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59° with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84°, DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81°, DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59° with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.
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| 6. |
- Angelov, Pavel, et al.
(författare)
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A 1.1-V Analog Multiplexer With an Adaptive Digital Clamp for CMOS Video Digitizers
- 2014
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 61:11, s. 860-864
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Tidskriftsartikel (refereegranskat)abstract
- We present the design of an integrated multiplexer and a dc clamp for the input analog interface of a high-speed video digitizer in the 1.1-V 65-nm complementary metal-oxide-semiconductor process. The ac-coupled video signal is dc restored using a novel all-digital current-mode charge pump. An eight-input multiplexer is realized with T-switches, each containing two series-connected bootstrapped switches. A T-switchs grounding branch is merged with the pull-down end of the clamping charge pump. An adaptive digital feedback loop encompassing a video analog-to-digital converter (ADC) controls the clamp charge pump. The bootstrapped switches have been adapted to suit the video environment, allowing on-the-fly recharging. The varying ON-resistance of the conventional bootstrapped switch is utilized to linearize the multiplexer response by canceling the effect of the nonlinear load capacitance contributed by the clamp transistors. Under worst case conditions, the multiplexer maintains a 62-85-dB spurious-free dynamic range over a range of known input video frequencies, and it reduces the second-order harmonic component upon optimization. The dc clamp provides 12-bit precision over the full range of the video ADC and can set the dc at the target level for at most 194 video lines.
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