SwePub - sökning: WFRF:(Alfredsson Jon 1977 )

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1.	Alfredsson, Jon, 1977-, et al. (författare) Basic Speed and Power Properties of Digital Floating-gate Circuits Operating in Subthreshold 2005 Ingår i: Proceedings of IFIP VLSI-SOC 2005. - : Edith Cowan Univ. ; , s. 229-232 Konferensbidrag (refereegranskat)abstract For digital circuits with ultra-low power consumption,floating-gate circuits have been considered to be a techniquepotentially better than standard static CMOS circuits.By having a DC offset on the floating gates, theeffective threshold voltage of the floating-gate transistoris adjusted and the speed and power performance can bealtered. In this paper the basic performance related propertiessuch as power, delay, power-delay product (PDP),and energy-delay product (EDP) for floating-gate circuitsoperating in subthreshold are investigated. Based on circuitsimulations in a 120nm process technology, it isshown that for the best case, the power can be reducedapproximately by one order of magnitude at the expenseof increased delay, while the PDP is more or less constantin comparison to static CMOS. The EDP can be reducedby two orders of magnitude at the expense of reducednoise margins.

Alfredsson, Jon, 1977-, et al. (författare)
Basic Speed and Power Properties of Digital Floating-gate Circuits Operating in Subthreshold
2005
Ingår i: Proceedings of IFIP VLSI-SOC 2005. - : Edith Cowan Univ. ; , s. 229-232
Konferensbidrag (refereegranskat)abstract
- For digital circuits with ultra-low power consumption,floating-gate circuits have been considered to be a techniquepotentially better than standard static CMOS circuits.By having a DC offset on the floating gates, theeffective threshold voltage of the floating-gate transistoris adjusted and the speed and power performance can bealtered. In this paper the basic performance related propertiessuch as power, delay, power-delay product (PDP),and energy-delay product (EDP) for floating-gate circuitsoperating in subthreshold are investigated. Based on circuitsimulations in a 120nm process technology, it isshown that for the best case, the power can be reducedapproximately by one order of magnitude at the expenseof increased delay, while the PDP is more or less constantin comparison to static CMOS. The EDP can be reducedby two orders of magnitude at the expense of reducednoise margins.

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