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- Alvandpour, A., et al.
(författare)
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A 3.5GHz 32mW 150nm Multiphase Clock Generator for High-Performance Microprocessors
- 2003
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Ingår i: Digest of Technical Papers. IEEE International Solid-State Circuits Conference, 9-13 February 2003. - 0193-6530. - 0780377079
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Konferensbidrag (refereegranskat)abstract
- A 3.5GHz 8-phase all-digital clock generator is fabricated in 150nm CMOS to achieve scalable 1.7x frequency-range and 9ps end-to-end time resolution measured at 1.6V and 110°C. A closed-to-open loop control scheme enables 32mW open-loop power consumption, 300μW at clock gate-off, zero-cycle response during clock re-enable, and
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| 5. |
- Krishnamurthy, Ram K., et al.
(författare)
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Low switching activity dynamic driver for high performance interconnects.
- 2002
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Patent (populärvet., debatt m.m.)abstract
- A high performance interconnect that utilizes dynamic driver technology is capable of reduced power operation during periods of low data switching activity. Circuitry is provided that limits the performance of an evaluation operation in the dynamic driver circuitry to clock cycles during which a present input bit of the interconnect differs from a previous input bit. Thus, the evaluation operation and subsequent precharge of the driver output is performed sparingly during periods of low data switching activity. An output circuit is also provided for decoding the data stream flowing through the interconnect at the receiver end thereof. Using the principles of the present invention, it is possible to achieve the performance advantages of dynamic drivers with the switching activity of interconnects that use static CMOS technology.
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| 6. |
- Vangal, Sriram, et al.
(författare)
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A 5.1GHz 0.34mm2 Router for Network-on-Chip Applications
- 2007
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Ingår i: 2007 IEEE Symposium on VLSI Circuits. - : IEEE. - 9784900784048 - 9784900784055 ; , s. 42-43
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Konferensbidrag (refereegranskat)abstract
- A five-port two-lane pipelined packet-switched router core with phase-tolerant mesochronous links forms the key communication fabric for an 80-tile network-on-chip (NoC) architecture. The 15FO4 design combines 102 GB/s of raw bandwidth with low fall-through latency of 980 ps. A shared crossbar architecture with a double-pumped crossbar switch enables a compact 0.34 mm2 router layout. In a 65nm eight-metal CMOS process, the router contains 210K transistors and operates at 5.1GHz at 1.2 V, while dissipating 945 mW.
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