| 1. |
- Abdulaziz, Mohammed, et al.
(författare)
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A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
- 2011
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Ingår i: [Host publication title missing]. - 9781457705144
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Konferensbidrag (refereegranskat)abstract
- A divider-less all digital phase locked loop (ADPLL) with a high frequency resolution is implemented. All blocks excluding digitally controlled oscillator (DCO) and time to digital converter (TDC) are realized in standard digital design which consumes less power. The DCO core adopts an improved source-varactor LC resonant tank to achieve a 20KHz frequency resolution. With the help of an additional ΔΣ modulator, the final frequency resolution is 625Hz. This work is simulated in 90nm CMOS process technology and consumes 7.6mW (DCO occupies 97.4%) under the power supply of 1.2V.
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| 2. |
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| 3. |
- Andersson, Mattias, et al.
(författare)
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A 7.5 mW 9 MHz CT Delta-Sigma Modulator in 65 nm CMOS with 69 dB SNDR and Reduced Sensitivity to Loop Delay Variations
- 2012
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Ingår i: IEEE Asian Solid State Circuits Conference (A-SSCC), 2012. ; , s. 245-248
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Konferensbidrag (refereegranskat)abstract
- This paper presents a 3rd-order, 3-bit continuous time (CT) Delta-Sigma modulator for an LTE radio receiver. By adopting a return-to-zero (RZ) pulse in the innermost DAC, the modulator shows a reduced sensitivity to loop-delay variations, and the additional loop delay compensation usually needed in CT modulators can be omitted. The modulator has been implemented in a 65nm CMOS process, where it occupies an area of 0.2mmx0.4mm. It achieves an SNR of 71dB and an SNDR of 69dB over a 9MHz bandwidth with an oversampling ratio of 16. Power consumption is 7.5mW from a 1.2V supply, for a figure-of-merit of 181fJ/conversion.
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| 4. |
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| 5. |
- Andersson, Mattias, et al.
(författare)
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A Filtering Delta Sigma ADC for LTE and Beyond
- 2014
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Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200. ; 49:7, s. 1535-1547
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Tidskriftsartikel (refereegranskat)abstract
- Abstract in UndeterminedThis paper presents a filtering ADC for the LTE communication standard, where a second-order Delta-Sigma modulator (DSM) is incorporated into the third-order Chebychev channel-select filter (CSF) of the radio receiver. The CSF introduces an additional third-order suppression of both thermal and quantization DSM noise, while the CSF transfer function is maintained. A design method for the filtering ADC accounting for unavoidable DSM-DAC delays is developed and experimentally demonstrated. The 65 nm CMOS prototype is clocked at 576/288 MHz with an 18.5/9.0 MHz LTE bandwidth, has an in-band gain of 26 dB, an SNDR of 56.4/58.1 dB, an input-referred noise of 5 nV/root Hz, and an out-of-band (half-duplex) IIP3 of 20/12 dBV(rms), with a power consumption of 7.9/5.4 mW and an overall state-of-the art performance.
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| 6. |
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| 7. |
- Andersson, Mattias, et al.
(författare)
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Theory and Design of a CT Delta Sigma Modulator with Low Sensitivity to Loop-Delay Variations
- 2013
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Ingår i: Analog Integrated Circuits and Signal Processing. - : Springer Science and Business Media LLC. - 0925-1030 .- 1573-1979. ; 76:3, s. 353-366
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a 3rd-order, 3-bit continuous-time (CT) \Updelta\Upsigma Δ Σ modulator for an LTE radio receiver. A return-to-zero (RZ) pulse, centered in the sampling period by a quadrature clock, is used in the innermost DAC to reduce the sensitivity to loop-delay variations in the modulator, and omit implementing the additional loop delay compensation usually needed in CT modulators. The performance and stability of the NRZ/NRZ/RZ feedback scheme is thoroughly analysed using a discrete-time model. The modulator has been implemented in a 65 nm CMOS process, where it occupies an area of 0.2 × 0.4 mm2. It achieves an SNR of 71 dB and an SNDR of 69 dB over a 9 MHz bandwidth with an oversampling ratio of 16, and a power consumption of 7.5 mW from a 1.2 V supply.
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| 8. |
- Andreani, Pietro, et al.
(författare)
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A 1.8-GHz CMOS VCO tuned by an accumulation-mode MOS varactor
- 2000
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Ingår i: The 2000 IEEE International Symposium on Circuits and Systems, 2000. Proceedings. ISCAS 2000.. - 0780354826 ; 1, s. 315-318
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Konferensbidrag (refereegranskat)abstract
- This work presents a 1.8-GHz VCO tuned by a pMOS capacitor working exclusively in the accumulation and depletion regions. The VCO has been fabricated in a standard 0.6 μm CMOS process. It shows a tuning range of about 11% and a phase noise of -137 dBc/Hz at 3 MHz offset from the carrier, for a current consumption of 2.7 mA. The VCO compares favorably with a CMOS VCO tuned by a reverse biased diode varactor
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| 9. |
- Andreani, Pietro, et al.
(författare)
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A 1.8 GHz CMOS VCO with reduced phase noise
- 2001
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Ingår i: 2001 Symposium on VLSI Circuits, 2001. Digest of Technical Papers.. - 4891140143 ; , s. 121-122
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Konferensbidrag (refereegranskat)abstract
- A 2 V, 6 mA, 15% tuning range, 1.8 GHz VCO implemented in a standard 0.35 μm CMOS process is presented. The phase noise of the VCO has been greatly reduced by means of on-chip filters and one off-chip low frequency inductor. The phase noise measured at 3 MHz offset from the carrier is between -141.5 dBc/Hz and -138.5 dBc/Hz over the whole tuning range
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| 10. |
- Andreani, Pietro
(författare)
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A 1.8-GHz monolithic CMOS VCO tuned by an inductive varactor
- 2001
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Ingår i: The 2001 IEEE International Symposium on Circuits and Systems, 2001. ISCAS 2001.. - 0780366859 ; 4, s. 714-717
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Konferensbidrag (refereegranskat)abstract
- A 1.8-GHz CMOS VCO is presented, employing a monolithic transformer as an inductance with voltage-controlled value. The design was implemented in a standard digital 0.6 μm, 2-metal CMOS process and exhibits a 10% tuning range with a 2.7 V supply voltage and a 9 mA supply current. Phase noise measurements show a worst-case phase noise of about -112 dBc/Hz at 3 MHz offset from the carrier
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