| 1. |
- Atallah, Jad G., et al.
(författare)
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A CMOS frequency synthesizer for multi-standard wireless devices
- 2003
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Ingår i: Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems. - NEW YORK : IEEE. - 0780382943 ; , s. 1138-1141
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Konferensbidrag (refereegranskat)abstract
- This paper presents a CMOS frequency synthesizer for wireless transceivers that support several communication standards namely GSM, WCDMA, IEEE 802.11b, and Bluetooth. The architecture is based on a multi-stage phase-locked loop where each stage differs from the others in the parameters of its charge pump and loop filter. It is designed using mathematical models and refined through simulation using different software tools depending on the required perspective. The architecture and the components presented pave the way to provide a low cost, fully integrated implementation.
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| 2. |
- Atallah, Jad. G., et al.
(författare)
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A direct conversion WiMAX RF receiver front-end in CMOS technology
- 2007
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Ingår i: ISSCS 2007. - NEW YORK : IEEE. - 9781424409686 ; , s. 37-40
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Konferensbidrag (refereegranskat)abstract
- This paper presents a direct conversion RF receiver front-end supporting the WiMAX standard. The front-end is implemented in 0.18um CMOS technology and designed using the ARCHER software. It shows how the design flow can be accelerated starting from the standard specifications and going down to schematics. All this is accompanied by test benches to extract the relevant metrics. This front-end provides a total gain of 31dB, a noise figure of 3.3dB, an IIP2 of 49.5dBm, and an IIP3 of -13.8dBm.
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| 3. |
- Atallah, Jad G., et al.
(författare)
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A frequency planning and generation scheme for multi-standard wireless transceivers
- 2005
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Ingår i: 12th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2005. - 9789972611001
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Konferensbidrag (refereegranskat)abstract
- This work presents a novel frequency planning scheme associated with a reference frequency generation scheme that has the potential of providing low phase noise contribution for several wireless standards including DCS1800, WCDMA II and III, DECT, WLAN a/b/g and Bluetooth. The scheme is particularly useful when implemented in future technologies and can be extended to cover newer wireless standards in newer bands of interest. It uses a single multi-band voltage-controlled oscillator (VCO) with switching inductors and high speed dividers directly generating the quadrature outputs. The VCO itself covers the frequency ranges from 4.8GHz to 6GHz and from 6.8GHz to 8GHz. Its phase noise is -136dBc/Hz at 1MHz offset from a center frequency of 1.85GHz. The design is sent for fabrication using 0.18ÎŒm CMOS.
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| 4. |
- Atallah, Jad G., et al.
(författare)
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Future 4G front-ends enabling smooth vertical handovers
- 2006
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Ingår i: IEEE Circuits & Devices. - 8755-3996 .- 1558-1888. ; 22:1, s. 6-15
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Tidskriftsartikel (refereegranskat)abstract
- An overview is given of the most important effects that handover considerations have on the design of multistandard mobile radio transceivers. Focus is on the multitude of design issues and challenges that should be taken into account in the RF/analog front-end part. Topics discussed include the convergence challenge, wireless transceiver design challenge, wireless standards, handover initiation, interworking between GSM and DECT, idle mode issues, possible issues when mobile terminals miss pages, procedure while in active communication in DECT mode, procedure while in active communication in GSM mode, and GSM/WLAN handover.
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| 5. |
- Atallah, Jad G., 1979-
(författare)
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Integrated Frequency Synthesis for Convergent Wireless Solutions
- 2008
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Wireless transceivers combining several standards in one unit are of key importance. In order to reach the ultimate goal of maximizing the performance-to-cost ratio of such modules, a careful study of the target application, the architecture, and the frequency planning is strongly required. One of the most challenging tasks is the implementation of the frequency synthesizer. This challenge is compounded by the traditional technical difficulties in designing frequency synthesizers as well as the new requirements that include multi-standard support. As a result, studying the upper levels of the communication system becomes mandatory in order to frame the requirements of the frequency synthesizer and to provide a viable solution from a user’s perspective for an always-best-connected scenario. Additionally, the study of the upper layers opens up new opportunities for innovation at the lower layers, especially at the physical layer where the view is traditionally restricted by some harsh requirements whose source might not be clear at least for the physical-level designer. The first aim of this work is to provide a holistic view of how an optimum user experience can be achieved and how this affects the design of frequency synthesizers for the next generation networks. The work is heavily based on the existing garden of wireless standards although it can also serve for other applications such as real software-defined radios and dynamic spectrum allocation. As a result, this work cuts a vertical path starting from the best user experience vision down to the physical layer where it expands on the design of the frequency synthesizer. It proposes a wireless front-end solution that can make the vision of an always-best-connected scenario a reality. The architecture is based on a wireless detector called Sniffer that searches for an alternative connection while the main connection is running. Not only is the Sniffer solution viable at the physical level, but it also provides a stepping stone for development towards fully-enabled multi-standard transceivers. After this, and inline with the previous vision, some important frequency synthesizer parameters are pointed out and enhancements on the phase-locked architectures are presented. This includes ways to extend the range of the frequency synthesizer and ways to make the synthesizer adaptable depending on the requirements of the wireless standards. This work leads directly to the implementation of a multi-standard frequency synthesizer where the details of the top-down design procedure are presented at several levels of abstraction. In order to round-up the work, and due to the fact that the requirements of the frequency synthesizer stretch thin the capabilities of the technology used, calibration techniques to increase the yield of such a complicated sub-system are presented, an important step towards first-pass success.
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| 6. |
- Bahramirad, S., et al.
(författare)
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A low phase noise VCO for multi band wireless transceivers
- 2007
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Ingår i: Proceedings - 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007. - : IEEE. - 1424412781 - 9781424412785 ; , s. 148-153
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Konferensbidrag (refereegranskat)abstract
- this paper presents a CMOS voltage controlled oscillator for multi standard wireless transceivers. The VCO structure is based on All- PMOS LC oscillators. The frequency range extends from 1.7 GHz to 2.5 GH, and tuning between frequencies is done by means of capacitor banks and varactors.
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| 7. |
- Dixon, A., et al.
(författare)
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Digital self-aware charge pump calibration technique for frequency synthesizers
- 2009
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Ingår i: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009. - : IEEE. - 9781424450916 ; , s. 743-746
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Konferensbidrag (refereegranskat)abstract
- As radio design complexity increases and features sizes decrease, more innovative solutions are explored to ensure analog circuit designs meet specifications. Digital calibration is an inexpensive and effective solution. A novel digital calibration technique to improve charge pump current mismatch in frequency synthesizers is presented. This method detect. The charge pump error by measurin. The low pass filter voltage oy the system forced to operate at a fixed phase error. A reference table developed from a mathematical model oy the system use. The measurement result to produce a digital control word. The digital control word acts on a charge pump array to correc. The error. The technique is implemented and tested in Matlab/Simulink for a case study frequency synthesizer. The calibration technique correct. The charge pump current absolute error to within 1.4% oy the nominal value. Additionally. The technique is exceptionally effective for correctin. The charge pump current mismatch to within 1%.
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| 8. |
- Rodriguez, Saul, et al.
(författare)
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A 2.3-GHz to 5.8-GHz CMOS receiver front-end for WiMAX/WLAN
- 2010
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Ingår i: 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings. - 9781424481552 ; , s. 1068-1071
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Konferensbidrag (refereegranskat)abstract
- This paper presents a wideband, direct-conversion radio receiver front-end that targets all WiMAX/WLAN bands from 2.3-GHz to 5.8-GHz. The receiver front-end is fabricated in 0.18-μm CMOS and achieves a gain of 25 dB, noise figure of 6 dB, and IIP3 of -6 dBm while dissipating 28 mW from a 1.8-V power supply. This performance is achieved while using only two integrated inductors.
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| 9. |
- Rodriguez, Saul, et al.
(författare)
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ARCHER : an automated RF-IC Rx front-end circuit design tool
- 2009
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Ingår i: Analog Integrated Circuits and Signal Processing. - : Springer Science and Business Media LLC. - 0925-1030 .- 1573-1979. ; 58:3, s. 255-270
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a tool capable of automatically compiling the circuit of a direct-conversion receiver at the schematics level based on system specifications that include the frequency of operation, gain, noise figure, IIP2 and IIP3 linearity. The front-end of a direct-conversion receiver is built using inductive source degeneration (LSD) LNA and double-balanced source-degenerated Gilbert Cell mixers with charge injection. The tool uses power constrained noise and linearity optimization vector-space algorithms that automatically size the transistors, passive components, and find the optimum biasing points. The solution generated by the tool is automatically read by Agilent ADS where the blocks are easily fine-tuned and validated before layout. Case studies involving WiMAX, UMTS, GSM, Bluetooth and WLAN are presented to reveal the capabilities of the tool in reducing the design time.
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| 10. |
- Rodriguez, Saul, et al.
(författare)
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ARCHER : An automated RF-IC Rx front-end circuit design tool
- 2007
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Ingår i: ISSCS 2007. - NEW YORK : IEEE. - 9781424409686 ; , s. 129-132
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Konferensbidrag (refereegranskat)abstract
- This paper presents a tool capable of compiling automatically the schematic circuit design of a direct conversion receiver based on system specifications including frequency of operation, gain, noise figured and 123 linearity. The rx front-end of a direct conversion receiver is built using inductive source degeneration (LSD) LNA and single-balanced source-degenerated Gilbert Cell mixers with charge injection. The tool uses power constrained noise and linearity optimization vector-space algorithms that size automatically the transistors, passive components, and finds the optimum biasing points. The solution generated by the tool is automatically read by Agilent ADS where the blocks are easily fine-tuned and validated before layout.
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