| 1. |
- Alfredsson, Jon, 1977-, et al.
(författare)
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Basic Speed and Power Properties of Digital Floating-gate Circuits Operating in Subthreshold
- 2005
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Ingår i: Proceedings of IFIP VLSI-SOC 2005. - : Edith Cowan Univ. ; , s. 229-232
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Konferensbidrag (refereegranskat)abstract
- For digital circuits with ultra-low power consumption,floating-gate circuits have been considered to be a techniquepotentially better than standard static CMOS circuits.By having a DC offset on the floating gates, theeffective threshold voltage of the floating-gate transistoris adjusted and the speed and power performance can bealtered. In this paper the basic performance related propertiessuch as power, delay, power-delay product (PDP),and energy-delay product (EDP) for floating-gate circuitsoperating in subthreshold are investigated. Based on circuitsimulations in a 120nm process technology, it isshown that for the best case, the power can be reducedapproximately by one order of magnitude at the expenseof increased delay, while the PDP is more or less constantin comparison to static CMOS. The EDP can be reducedby two orders of magnitude at the expense of reducednoise margins.
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| 2. |
- Alfredsson, Jon, et al.
(författare)
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D-latch for Subthreshold Floating-Gate Circuits Exploiting Threshold Elements
- 2007
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Ingår i: 2007 NORCHIP. - : IEEE conference proceedings. - 9781424415168 ; , s. 146-149
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Konferensbidrag (refereegranskat)abstract
- When power supply for circuits is reduced the performance will also drop accordingly and to keep up the performance while lowering power supply is an important issue. Floating-gate circuits (FGMOS) have previously been simulated with low power supply and basic digital gates and circuits have already been designed and studied to determine speed and power performance. In this paper we try to expand the circuit library for subthreshold power supply FGMOS circuits by including a floating-gate memory element in terms of a D-latch. Our simulations at 250 mV power supply of a FGMOS D-latch are compared with other D-latches based on static CMOS and mirrored gate elements. The simulations we have performed shows that static CMOS has an advantage in performance of several orders of magnitude in terms of power consumption, while PDP and EDP performance are also better than for FGMOS. When it comes to speed performance, we show that the FGMOS D-latch can be up to 18 times faster than CMOS at the expense of up to three orders of magnitude higher power consumption.
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| 3. |
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| 4. |
- Alfredsson, Jon, et al.
(författare)
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Performance of CMOS and floating-gate full-adders circuits at subthreshold power supply
- 2007
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Ingår i: Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation. - Berlin : Springer. - 9783540744412 ; , s. 536-546
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Konferensbidrag (refereegranskat)abstract
- To reduce power consumption in electronic designs, new techniques for circuit design must always be considered. Floating-gate MOS (FGMOS) is one of those techniques and has previously shown potentially better performance than standard static CMOS circuits for ultra-low power designs. One reason for this is because FGMOS only requires a few transistors per gate and still retain a large fan-in. Another reason is that CMOS circuits becomes very slow in subthreshold region and are not suitable in many applications while FGMOS can have a shift in threshold voltage to increase speed performance. This paper investigates how the performance of an FGMOS full-adder circuit will compare with two common CMOS full-adder designs. Simulations in a 120 nm process shows that FGMOS can have up to 9 times better EDP performance at 250 mV. The simulations also show that the FGMOS full-adder is 32 times faster and have two orders of magnitude higher power consumption than that for CMOS.
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| 5. |
- Alfredsson, Jon, et al.
(författare)
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Pseudo floating-gate design limitations in Nano-CMOS with low power supply
- 2008
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Ingår i: Proceedings of IFIP VLSI-SOC Conference 2008.
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Konferensbidrag (refereegranskat)abstract
- This paper shows simulation results from a recentlyproposed Pseudo Floating-Gate (PFG) technique for use insubthreshold. The design and simulations is performed in a 120nm process CMOS technology and show that there arelimitations that will make subthreshold PFG very difficult tomanufacture with full functionality. The simulations showlimitations in fan-in that will contribute to making it harder tomanufacture structures that have small area or a higharithmetic complexity per active element. It also showbandwidth limitations for the input and output signals.As a complement to the simulations of our PFG design we havealso made a summary of several different kinds of PFGtechniques that are previously developed and some of theirlimitations. The summary also tries to determine where thePFG techniques originates from and present an overview of themost obvious limitations they have.
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| 6. |
- Alfredsson, Jon, et al.
(författare)
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Small Fan-in Floating-gate Circuits with Application to an Improved Adder Structure
- 2007
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Ingår i: 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS - TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA. - : IEEE conference proceedings. - 9780769527628 ; , s. 314-317
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Konferensbidrag (refereegranskat)abstract
- For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. One reason for this is because FGMOS only requires a few transistors per gate while it still can have a large fan-in. When power supply is reduced to subthreshold region it will influence the maximum fan-in that is possible to use in designs. In this paper we have investigated how the performance of FGMOS circuits will change in subthreshold region. Simulation in a 120 nm process technology shows that FGMOS will not be working for circuits that have a large fan-in and might not be useable for many designs. At 250 mV power supply it can have a maximum fan-in of 5 and for 150 mV the maximum is 3. FGMOS simulations of an improved full-adder structure with fan-in of 3 is also proposed and compared to a conventional structure with fan-in of 5. It is shown that the improved full-adder with fan-in 3 will have more than 36 times better energy-delay product (EDP)
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| 7. |
- Alfredsson, Jon, et al.
(författare)
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Trade-offs for high yield in 90 nm subthreshold floating-gate circuits by Monte Carlo simulations
- 2008
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Ingår i: Proceedings of IFIP VLSI-SOC Conference 2008.
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Konferensbidrag (refereegranskat)abstract
- The work described in this paper is performed toestimate the influence of statistical process variations andtransistor mismatch that occurs in fabrication and affectfloating-gate digital circuits. These effects will affect and reduce“yield” (percentage of fully functional circuits). Monte Carlosimulations have been performed in a 90 nm to estimate theyield for manufactured floating-gate circuits running withsubthreshold power supply. The power supply, floating-gatecharge voltage (VFGP and VFGN) and transistor sizes have beenvaried during the simulations and the yield has been observed.The simulation results shows that by doubling the minimumsize transistors (length and width) the yield can be much betterthan for minimum size version. A yield of 100% can though notbe expected if the power supply is scaled down below 250 mV.
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| 8. |
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| 9. |
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| 10. |
- Aunet, Snorre, et al.
(författare)
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Real-time reconfigurable subthreshold CMOS perceptron
- 2008
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Ingår i: IEEE Transactions on Neural Networks. - 1045-9227 .- 1941-0093. ; 19:4, s. 645-657
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, a new, real-time reconfigurable perceptron circuit element is presented. A six-transistor version used as a threshold gate, having a fan-in of three, producing adequate outputs for threshold of T = 1, 2 and 3 is demonstrated by chip measurements. Subthreshold operation for supply voltages in the range of 100-350 mV is shown. The circuit performs competitively with a standard static complimentary metal-oxide-semiconductor (CMOS) implementation when maximum speed and energy delay product are taken into account, when used in a ring oscillator. Functionality per transistor is, to our knowledge, the highest reported for a variety of comparable circuits not based on floating gate techniques. Statistical simulations predict probabilities for making working circuits under mismatch and process variations. The simulations, in 120-nm CMOS, also support discussions regarding lower limits to supply voltage and redundancy. A brief discussion on bow the circuit may be exploited as a basic building block for future defect tolerant mixed signal circuits, as well as neural networks, exploiting redundancy, is included.
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