| 1. |
- Börjeson, Erik, 1984, et al.
(författare)
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ASIC Design Exploration of Phase Recovery Algorithms for M-QAM Fiber-Optic Systems
- 2019
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Ingår i: Optics InfoBase Conference Papers. - 2162-2701. - 9781943580538
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Konferensbidrag (refereegranskat)abstract
- We develop circuit implementations and explore design optimizations for one blind and one pilot-based carrier phase-recovery algorithm, where the former algorithm is shown to dissipate 1.8-4.5 pJ/bit and the latter 0.5-0.3 pJ/bit, using 16 to 256QAM.
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| 2. |
- Börjeson, Erik, 1984, et al.
(författare)
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Benchmarking of Carrier Phase Recovery Circuits for M-QAM Coherent Systems
- 2021
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Ingår i: Optical Fiber Communication Conference, OFC 2021. - 9781943580866 - 9781557528209
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Konferensbidrag (refereegranskat)abstract
- We benchmark blind carrier phase recovery DSP circuits in terms of SNR penalty, power dissipation, latency, area usage, and cycle slip probability, to identify optimal implementations for 16, 64, and 256QAM.
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| 3. |
- Börjeson, Erik, 1984, et al.
(författare)
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Circuit Implementation of Pilot-Based Dynamic MIMO Equalization for Coupled-Core Fibers
- 2024
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Ingår i: Optical Fiber Communication Conference, OFC 2024. - 9781957171326
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Konferensbidrag (refereegranskat)abstract
- We explore ASIC implementation for pilot-based MIMO equalizers for coupled-core transmission, considering chip area scaling trends and performance impact of time-dependent drift. For a system with 28-GBd subcarriers, an equalizer for 8 × 8 is 5.3 times larger than for 2 × 2.
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| 4. |
- Börjeson, Erik, 1984, et al.
(författare)
-
Cycle-Slip Rate Analysis of Blind Phase Search DSP Circuit Implementations
- 2020
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Ingår i: 2020 Optical Fiber Communications Conference and Exhibition, OFC 2020 - Proceedings. - 9781943580712
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Konferensbidrag (refereegranskat)abstract
- Using FPGA-accelerated simulations, we study the cycle-slip rate of 16QAM blind phase search implementations. While block averaging suffers from degraded BER when compared to sliding-window averaging, it results in lower cycle-slip rates and power dissipation.
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| 5. |
- Börjeson, Erik, 1984, et al.
(författare)
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Energy-Efficient Implementation of Carrier Phase Recovery for Higher-Order Modulation Formats
- 2021
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Ingår i: Journal of Lightwave Technology. - 0733-8724 .- 1558-2213. ; 39:2, s. 505-510
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Tidskriftsartikel (refereegranskat)abstract
- We introduce circuit implementations of one- and two-stage carrier phase recovery (CPR) for 256QAM coherent optical receivers. We describe in detail the optimizations of algorithms, such as modified Viterbi-Viterbi (mVV), blind phase search (BPS), and principal component-based phase estimation (PCPE), that are required to develop energy-efficient CPR circuits and show how design parameter settings and limited fixed-point resolution affect the SNR penalty. 30-GBaud CPR circuit netlists synthesized in a 22-nm CMOS process technology allow us to study trade-offs between energy per bit and SNR penalty. We show that it is possible to reach an energy dissipation of around 1 pJ/bit at an SNR penalty of 0.6 dB for two-stage PCPE+BPS and mVV+BPS implementations, and that PCPE+BPS is the preferred choice thanks to its smaller area.
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| 6. |
- Börjeson, Erik, 1984, et al.
(författare)
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Fiber-on-Chip: Digital Emulation of Channel Impairments for Real-Time DSP Evaluation
- 2023
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Ingår i: Journal of Lightwave Technology. - 0733-8724 .- 1558-2213. ; 41:3, s. 888-896
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Tidskriftsartikel (refereegranskat)abstract
- We describe the Fiber-on-Chip (FoC) approach to verification of digital signal processing (DSP) circuits, where digital models of a fiber-optic communication system are implemented in the same hardware as the DSP under test. The approach can enable cost-effective long-term DSP evaluations without the need for complex optical-electronic testbeds with high-speed interfaces, shortening verification time and enabling deep bit-error rate evaluations. Our FoC system currently contains a digital model of a transmitter generating a pseudo-random bitstream and a digital model of a channel with additive white Gaussian noise, phase noise and polarization-mode dispersion. In addition, the FoC system contains digital features for real-time control of channel parameters, using low-speed communication interfaces, and for autonomous real-time analysis, which enable us to batch multiple unsupervised emulations on the same hardware. The FoC system can target both field-programmable gate arrays, for fast evaluation of fixed-point logic, and application-specific integrated circuits, for accurate power dissipation measurements.
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| 7. |
- Börjeson, Erik, 1984
(författare)
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Implementation and Evaluation of Signal Processing Circuits for Optical Communication
- 2024
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The digital signal processing (DSP) circuits used in the fiber-optic communication links that make up the backbone of the Internet can be a significant contributor the over-all power dissipation of a link. As the number of connected users and their bandwidth requirements are expected to continue to grow over the coming years, the development of power-efficient high-throughput DSP systems is a critical factor in enabling this growth. Unfortunately, DSP designers can no longer depend on foundries delivering faster and more power-efficient circuits for each new process node, due to both economical and physical limitations. As a result, more stringent speed and power requirements are put on the circuit designs. Carrier phase recovery (CPR) is one subsystem of a typical DSP system for fiber-optic communication. In this thesis, we explore and evaluate circuit designs of multiple types of CPR, with a focus on single-mode systems. The circuit designs allow us to uncover trade-offs between power dissipation, area, throughput and signal degradation, for different types of systems employing a range of modulation formats. Coupled-core multi-mode fiber systems have been suggested as a way to increase throughput by utilizing also the spatial dimension, and this thesis describes a multiple-input multiple-output adaptive equalizer targeting these systems. The equalizer circuit enables exploration of how this critical subsystem scales to higher core counts. Additionally, we describe a circuit verification and evaluation environment that has the potential to speed up simulations by orders of magnitude by emulating a fiber-optic link onboard an application-specific integrated circuit or a field-programmable gate array.
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| 8. |
- Börjeson, Erik, 1984
(författare)
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Implementation of Carrier Phase Recovery Circuits for Optical Communication
- 2020
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Fiber-optic links form a vital part of our increasingly connected world, and as the number of Internet users and the network traffic increases, reducing the power dissipation of these links becomes more important. A considerable part of the total link power is dissipated in the digital signal processing (DSP) subsystems, which show a growing complexity as more advanced modulation formats are introduced. Since DSP designers can no longer take reduced power dissipation with each new CMOS process node for granted, the design of more efficient DSPalgorithms in conjunction with circuit implementation strategies focused on power efficiency is required. One part of the DSP for a coherent fiber-optic link is the carrier phase recovery (CPR) unit, which can account for a significant portion of the DSP power dissipation, especially for shorter links. A wide range of CPR algorithms is available, but reliable estimates of their power efficiency is missing, making accurate comparisons impossible. Furthermore, much of the current literature does not account for the limited precision arithmetic of the DSP. In this thesis, we develop circuit implementations based on a range of suggested CPR algorithms, focusing on power efficiency. These circuits allow us to contrast different CPR solutions based not only on power dissipation, but also on the quality of the phase estimation, including fixed-point arithmetic aspects. We also show how different parameter settings affect the power efficiency and the implementation penalty. Additionally, the thesis includes a description of our field-programmable gate-array fiber-emulation environment, which can be used to study rare phenomena in DSP implementations, or to reach very low bit-error rates. We use this environment to evaluate the cycle-slip probability of a CPR implementation.
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| 9. |
- Börjeson, Erik, 1984, et al.
(författare)
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Multi-Format Carrier Phase Recovery Using a Programmable Circuit
- 2021
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Ingår i: Optics InfoBase Conference Papers.
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Konferensbidrag (refereegranskat)abstract
- We introduce an application-specific circuit that can be programmed to efficiently perform blind carrier phase recovery for different modulation formats. A circuit implementation that supports QPSK/16/32/64QAM is evaluated.
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| 10. |
- Börjeson, Erik, 1984, et al.
(författare)
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Real-Time Implementation of Machine-Learning DSP
- 2024
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Ingår i: 2024 Optical Fiber Communications Conference and Exhibition, OFC 2024 - Proceedings.
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Konferensbidrag (refereegranskat)abstract
- While ML algorithms can learn and adapt to channel characteristics, implementation of ML-based DSP hardware is challenging. We demonstrate a real-time implementation of a model-based ML equalizer that compensates a non-linear and time-varying channel.
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