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| 2. |
- Svensson, Bertil, 1948-, et al.
(författare)
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A running leap for embedded signal processing to future parallel platforms
- 2014
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Ingår i: WISE 2014 - Proceedings of the 2014 ACM International Workshop on Long-Term Industrial Collaboration on Software Engineering, Co-located with ASE 2014. - New York, NY, USA : Association for Computing Machinery, Inc. - 9781450330459 ; , s. 35-42
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Konferensbidrag (refereegranskat)abstract
- This paper highlights the collaboration between industry and academia in research. It describes more than two decades of intensive development and research of new hardware and software platforms to support innovative, high-performance sensor systems with extremely high demands on embedded signal processing capability. The joint research can be seen as the run before a necessary jump to a new kind of computational platform based on parallelism. The collaboration has had several phases, starting with a focus on hardware, then on efficiency, later on software development, and finally on taking the jump and understanding the expected future. In the first part of the paper, these phases and their respective challenges and results are described. Then, in the second part, we reflect upon the motivation for collaboration between company and university, the roles of the partners, the experiences gained and the long-term effects on both sides.
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| 3. |
- Bengtsson, Jerker, et al.
(författare)
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A configurable framework for stream programming exploration in baseband applications
- 2006
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Ingår i: 2006 IEEE International Parallel & Distributed Processing Symposium. - Piscataway, N.J. : IEEE Press. - 1424400546 ; , s. 8-
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Konferensbidrag (refereegranskat)abstract
- This paper presents a configurable framework to be used for rapid prototyping of stream based languages. The framework is based on a set of design patterns defining the elementary structure of a domain specific language for high-performance signal processing. A stream language prototype for baseband processing has been implemented using the framework. We introduce language constructs to efficiently handle dynamic reconfiguration of distributed processing parameters. It is also demonstrated how new language specific primitive data types and operators can be used to efficiently and machine independently express computations on bitfields and data-parallel vectors. These types and operators yield code that is readable, compact and amenable to a stricter type checking than is common practice. They make it possible for a programmer to explicitly express parallelism to be exploited by a compiler. In short, they provide a programming style that is less error prone and has the potential to lead to more efficient implementations.
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| 4. |
- Bengtsson, Jerker, et al.
(författare)
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A Domain-specific Approach for Software Development on Manycore Platforms
- 2008
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Ingår i: SIGARCH Computer Architecture News. - New York : ACM Press. - 0163-5964 .- 1943-5851. ; 36:5, s. 2-10
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Tidskriftsartikel (refereegranskat)abstract
- The programming complexity of increasingly parallel processors calls for new tools that assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed as part of a tool for mapping dataflow graphs onto manycores. One of the models captures the essentials of manycores identified as suitable for signal processing, and which we use as target for our algorithms. As an intermediate representation we introduce timed configuration graphs, which describe the mapping of a model of an application onto a machine model. Moreover, we show how a timed configuration graph by very simple means can be evaluated using an abstract interpretation to obtain performance feedback. This information can be used by our tool and by the programmer in order to discover improved mappings.
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| 5. |
- Bengtsson, Jerker
(författare)
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Baseband Processing in 3G UMTS Radio Base Stations
- 2006
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Rapport (övrigt vetenskapligt/konstnärligt)abstract
- This report presents a study of functionality, service dataflows, computation characteristics and processing parameters for baseband processing in radio base stations. The study has been performed with the objective to develop a programming model that is natural and efficient to use for baseband programming and which can be efficiently compiled to parallel computing structures. In order to achieve this objective it is necessary to analyse and understand the logical architecture of the application in order to be able to define processing characteristics and thereby requirements on languages as well as on physical system architectures. Moreover, to be able to test and verify programming and mapping of functions it is necessary to have realistic but still manageable test cases. The study is focused on the third generation partnership project (3GPP) standard specifications for 3G radio base stations. The specifications cover the complete 3G network-architecture and are quite extensive and complex. To make experiments manageable, it is necessary to abstract system functionality that is not directly relevant for the RBS baseband processing. Moreover, the standard specifications only describe the required processing functionality on an abstract logical level. In this report, the functionality of the baseband functions is explained and also described using illustrations of dataflows and abstract mapping of two 3G service cases. The results of the study constitute a comprehensive description of the processing flow and the mapping of user data channels in 3G radio base stations – spanning data and control input from layer 2 to physical channel output from layer 1. Data dependencies between functions are illustrated with figures and it is concluded that these dependencies are of producer/consumer type. It is discussed how different functions can be mapped in MIMD and SIMD fashion with regard to the data dependencies, the data stream lengths and the control operations required to handle bit stream processing on word-length processor architectures.
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| 6. |
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| 7. |
- Bengtsson, Jerker
(författare)
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Efficient implementation of stream applications on processor arrays
- 2006
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- This thesis concludes work conducted on exploring the usage of parallel and reconfigurable processor architectures in industrial high-performance embedded systems. This kind of systems has by tradition been built using a mix of digital signal processors and custom made hardware. Digital signal processors provide full functional felxibility, but at the cost of lower performance. Custom made hardware can be optimized for specific functions for high performance, but at the cost of inflexibility and high development costs. A desire is to combine flexibility and performance using commercial hardware, without trading too much of performance for flexibility.Parallel and reconfigurable architectures provide a flexible computing space constituting processing elements that are coupled through configurable communication structures. Architectures designed with less complex processing elements render a high degree of utilizable parallelism at the cost of having to use a portion of the pocessing elements for control functions. In the thesis it is shown that it is possible to utilize this kind of architecture to achieve high performance efficiency, despite the fact that a large fraction of PEs are required to implement control-oriented portions in a fairly complex algorithm.A major problem is that architectures of this kind expose a very complex programming abstraction for compilers and programmers. The approach taken in this work is a domain-specific stream processing model which provides means to express application-specific dataflows and computations in terms of streams. An extensive application study comprising the baseband processing in radio base stations has been used to define sufficient data types, operators and language construct. Furthermore, to support industrial requirements on portability to different architectures, it must be possible to express parallelism and characteristic computations without exposing of hardware details in the source code.To be able to prototype and set up experiments with stream processing languages an experimental programming framework has been developed. A first prototype language with specific primitive types, operators and stream constructs has been implemented in order to elaborate with baseband programming. It is demonstrated how these types and operators can be used to express machine-independent bit field and other fine-grained data parallel computations. Furthermore, the language has been designed with constructs for efficient and flexible programming of reconfiguration of distributed function parameters.
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| 8. |
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| 9. |
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| 10. |
- Bengtsson, Jerker, et al.
(författare)
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Manycore performance analysis using timed configuration graphs
- 2009
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Ingår i: International Symposium on Systems, Architectures, Modeling, and Simulation, 2009. SAMOS '09. - Piscataway, N.J. : IEEE Press. - 9781424445028 ; , s. 108-117
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Konferensbidrag (refereegranskat)abstract
- The programming complexity of increasingly parallel processors calls for new tools to assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed to form part of a tool which is intended for iteratively tuning the mapping of dataflow graphs onto manycores. One of the models is used for capturing the essentials of manycores that are identified as suitable for signal processing and which we use as target architectures. Another model is the intermediate representation in the form of a timed configuration graph, describing the mapping of a dataflow graph onto a machine model. Moreover, this IR can be used for performance evaluation using abstract interpretation. We demonstrate how the models can be configured and applied in order to map applications on the Raw processor. Furthermore, we report promising results on the accuracy of performance predictions produced by our tool. It is also demonstrated that the tool can be used to rank different mappings with respect to optimisation on throughput and end-to-end latency.
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