| 1. |
- Bezati, Endri, et al.
(författare)
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Clock-gating of streaming applications for energy efficient implementations on FPGAs
- 2016
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Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - 0278-0070. ; , s. 699-703
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Tidskriftsartikel (refereegranskat)abstract
- The paper investigates the reduction of dynamic power for streaming applications yielded by asynchronous dataflow designs by using clock gating techniques. Streaming applications constitute a very broad class of computing algorithms in areas such as signal processing, digital media coding, cryptography, video analytics, network routing and packet processing and many others. The paper introduces a set of techniques that, considering the dynamic streaming behavior of algorithms, can achieve power savings by selectively switching off parts of the circuits when they are temporarily inactive. The techniques being independent from the semantic of the application can be applied to any application and can be integrated into the synthesis stage of a high-level dataflow design flow. Experimental results of atsize applications synthesized on FPGAs platforms demonstrate power reductions achievable with no loss in data throughput.
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| 2. |
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| 3. |
- Bezati, Endri, et al.
(författare)
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High-level Synthesis of Dataflow Programs for Signal Processing Systems
- 2013
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Konferensbidrag (refereegranskat)abstract
- The growing complexity of signal processing algorithms and platforms poses significant challenges to design methods and implementation tools. High-level dataflow programs, such as those in MPEG's RVC-CAL language, provide abstraction and the opportunity for extensive design-space exploration, but they do raise the problem of efficient automatic synthesis to hardware and software. This paper presents a tool called Xronos that efficiently synthesizes RVC-CAL programs to an RTL-level hardware description and significantly improves on previous efforts in both quality of the resulting implementation and synthesis speed. By directly supporting all the features of the RVC-CAL language, it translates unmodified standard MPEG reference code to a functioning hardware implementation. The paper describes the essential processing architecture of Xronos, the differences from other related approaches and experimental results that show Xronos to produce faster and smaller implementations, while at the same time significantly reducing synthesis times
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| 4. |
- Bezati, Endri, et al.
(författare)
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High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms
- 2016
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Ingår i: 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS). - 9781509030774 - 9781509030767 ; , s. 227-234
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Konferensbidrag (refereegranskat)abstract
- The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on programmable logic devices and embedded processors. Past research has shown that, for complex systems, raising the level of abstraction of design stages does not necessarily come at a penalty in terms of performance or resource requirements. Dataflow programs provide behavioral descriptions capable of expressing both sequential and parallel components of application algorithms and enable natural design abstractions, modularity, and portability. In this paper, an open source tool, implementing dataflow programs onto embedded heterogeneous platforms by means of high-level synthesis, software synthesis and interface synthesis is presented Experimental design results demonstrate the capability and the effectiveness of the tool for implementing a wide range of applications when combined with Vivado HLS.
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| 5. |
- Bezati, Endri, et al.
(författare)
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High-level system synthesis and optimization of dataflow programs for MPSoCs
- 2017
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Ingår i: 50th Asilomar Conference on Signals, Systems and Computers, ACSSC 2016. - 9781538639542 ; , s. 417-421
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Konferensbidrag (refereegranskat)abstract
- The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on reconfigurable and embedded devices. Past research has shown that raising the level of abstraction of design stages does not necessarily gives penalties in terms of performance or resources. Dataflow programs provide behavioral descriptions capable of expressing both sequential and parallel algorithms and enable natural design abstractions, modularity, and portability. In this paper, a tool implementing dataflow programs onto embedded heterogeneous platforms by means of high-level synthesis, software synthesis and interface synthesis is presented for MPSoCs platfroms.
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| 6. |
- Bezati, Endri, et al.
(författare)
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Synthesis and optimization of high-level stream programs
- 2013
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Ingår i: Proceedings of the Electronic System Level Synthesis Conference (ESLsyn). - 9782953998795 - 9781467364140
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Konferensbidrag (refereegranskat)abstract
- In this paper we address the problem of translating high-level stream programs, such as those written in MPEG's RVC-CAL dataflow language, into implementations in programmable hardware. Our focus is on two aspects: sufficient language coverage to make synthesis available for a large class of programs, and methodology and tool support providing analysis and guidance to improve and optimize an initial implementation. Our main results are (1) a synthesis tool that for the first time translates a complete and unmodified MPEG reference implementation into a working hardware description, and (2) a suite of profiling and analysis tools that analyze the structure of computation weighted by data obtained from the synthesis process, and accurately pinpoint parts of the program that are targets for optimization.
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| 7. |
- Brunet, Simone Casale, et al.
(författare)
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Design space exploration and implementation of RVC-CAL applications using the TURNUS framework
- 2013
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Ingår i: 2013 Conference on Design and Architectures for Signal and Image Processing (DASIP). - 1966-7116. - 9791092279023 ; , s. 341-342
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Konferensbidrag (refereegranskat)abstract
- While research on the design of heterogeneous concurrent systems has a long and rich history, a unified design methodology and tool support has not emerged so far, and thus the creation of such systems remains a difficult, time-consuming and error-prone process. The absence of principled support for system evaluation and optimization at high abstraction levels makes the quality of the resulting implementation highly dependent on the experience or prejudices of the designer. In this work we present TURNUS, a unified dataflow design space exploration framework for heterogeneous parallel systems. It provides high-level modelling and simulation methods and tools for system level performances estimation and optimization. TURNUS represents the outcome of several years of research in the area of co-design exploration for multimedia stream applications. During the presentation, it will be demonstrated how the initial high-level abstraction of the design facilitates the use of different analysis and optimization heuristics. These guide the designer during validation and optimization stages without requiring low-level implementations of parts of the application. Our framework currently yields exploration and optimization results in terms of algorithmic optimization, rapid performance estimation, application throughput, buffer size dimensioning, and power optimization
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| 8. |
- Canala, Massimo, et al.
(författare)
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Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling
- 2014
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Ingår i: [Host publication title missing]. ; , s. 1-6
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Konferensbidrag (refereegranskat)abstract
- This paper presents a new approach to buffer dimensioning for dynamic dataflow implementations. A novel transformation applied to the execution trace graph of a dataflow program is introduced in order to generate an event driven system. It is shown how model predictive control theory techniques can be applied to such a system to analyse the execution space of a dataflow program and to define and to minimize a bounded buffer size configuration that corresponds to a deadlock free execution. Some experimental results obtained using two design examples, i.e. a JPEG and an MPEG HEVC decoder, are reported and compared to the state of the art results in order to show the effectiveness of the introduced approach.
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| 9. |
- Casale Brunet, Simone, et al.
(författare)
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Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control
- 2014
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Ingår i: [Host publication title missing]. ; , s. 1-6
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Konferensbidrag (refereegranskat)abstract
- Execution trace graph analysis of dataflow programs has been demonstrated to be an effective way for exploring and optimizing the design space of many core applications. In this work a novel transformation from the execution trace graph to an event driven linear system is proposed. It is also illustrated how the trace space of can be effectively reduced and well known system control techniques can be efficiently used in order to find close to optimal solutions. In particular, the problem of finding a bounded buffer size configuration is proposed and solved using a model predictive controller. Two design examples, a JPEG and an MPEG HEVC decoder have been used to demonstrate the effectiveness of the approach.
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| 10. |
- Casale Brunet, Simone, et al.
(författare)
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Turnus: An open-source design space exploration framework for dynamic stream programs
- 2014
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Ingår i: [Host publication title missing]. ; , s. 1-2
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Konferensbidrag (refereegranskat)abstract
- Although the research on the design of heterogeneous concurrent systems has a long and rich history, a unified design methodology and tool support have not emerged so far. Therefore, the creation of such systems remains a difficult, time-consuming and error-prone process. The absence of principled support for system evaluation and optimization at high level of abstraction makes the quality of the resulting implementation strongly dependent on the experience or individual preferences of the designer. In this work we are presenting TURNUS, a unified dataflow design space exploration framework for heterogeneous parallel systems. This open source framework represents a decade of research on high-level modelling and simulation methods and tools for system level performance estimation and optimization. Last year we presented heuristic algorithms that were focused on the results of exploration in terms of algorithmic optimization, rapid performance estimation, application throughput, buffer size dimensioning and power optimization. This year we are presenting the novelties that have been introduced in TURNUS such as clock gating, pipelining optimization, kernel splitting algorithms, advanced partitioning algorithms and scheduling optimization based on model predictive control techniques.
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