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| 2. |
- Alvandpour, A., et al.
(författare)
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A 3.5GHz 32mW 150nm Multiphase Clock Generator for High-Performance Microprocessors
- 2003
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Ingår i: Digest of Technical Papers. IEEE International Solid-State Circuits Conference, 9-13 February 2003. - 0193-6530. - 0780377079
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Konferensbidrag (refereegranskat)abstract
- A 3.5GHz 8-phase all-digital clock generator is fabricated in 150nm CMOS to achieve scalable 1.7x frequency-range and 9ps end-to-end time resolution measured at 1.6V and 110°C. A closed-to-open loop control scheme enables 32mW open-loop power consumption, 300μW at clock gate-off, zero-cycle response during clock re-enable, and
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| 3. |
- Krishnamurthy, R.K., et al.
(författare)
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High-performance, low-power, and leakage-tolerance challenges for sub-70nm microprocessor circuits
- 2002
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Ingår i: Proceedings fo the 28th European Solid-Stated Circuits Conference. ; , s. 315-321
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Konferensbidrag (refereegranskat)abstract
- CMOS technology scaling is becoming difficult beyond 70nm node, raising new design challenges for high-performance and low-power microprocessors. This paper discusses some of the key paradigm shifts required. Circuit techniques to combat (i) increasing switching and leakage power dissipation, (ii) poor leakage tolerance of large-signal cache arrays and register files, (iii) worsening global on-chip interconnect scaling trend, and (iv) high-performance robust datapath circuits enabling up to 10GHz ALU and instruction scheduler loops in 130nm dual-Vt CMOS technology are described.
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| 6. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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A Low-Leakage Dynamic Multi-Ported Register file in 0.13mm CMOS
- 2001
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Ingår i: ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design. - New York, USA : ACM. - 1581133715 ; , s. 68-71
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Konferensbidrag (refereegranskat)abstract
- Increasing leakage currents combined with reduced noise margins are seriously degrading the robustness of dynamic circuits. This paper describes a dynamic implementation of a 256X32b 4-read/write-port Register-File for ~6GHz operation at 1.2V in a 0.13 utilize an efficient conditional keeper-technique, where a large fraction of the keeper is turned remains are able to improve upon all-low-Vt performance by 4%, while maintaining Dual-Vt usage. Thus, the robustness is improved by 96% and the active leakage power is reduced by 5X.
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| 7. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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A sub-130-nm conditional keeper technique
- 2002
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Ingår i: IEEE Journal of Solid-State Circuits. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9200 .- 1558-173X. ; 37:5, s. 633-638
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Tidskriftsartikel (refereegranskat)abstract
- Increasing leakage currents combined with reduced noise margins significantly degrade the robustness of wide dynamic circuits. In this paper, we describe two conditional keeper topologies for improving the robustness of sub-130-nm wide dynamic circuits. They are applicable in normal mode of operation as well as during burn-in test. A large fraction of the keepers is activated conditionally, allowing the use of strong keepers with leaky precharged circuits without significant impact on performance of the circuits. Compared to conventional techniques, up to 28% higher performance has been observed for wide dynamic gates in a 130-nm technology. In addition, the proposed burn-in keeper results in 64% active area reduction
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| 10. |
- Krishnamurthy, R.K., et al.
(författare)
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A 130-nm 6-GHz 256x32 bit leakage-tolerant register file
- 2002
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Ingår i: IEEE Journal of Solid-State Circuits. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9200 .- 1558-173X. ; 37:5, s. 624-632
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Tidskriftsartikel (refereegranskat)abstract
- Describes a 256-word × 32-bit 4-read, 4-write ported register file for 6-GHz operation in 1.2-V 130-nm technology. The local bitline uses a pseudostatic technique for aggressive bitline active leakage reduction/tolerance to enable 16 bitcells/bitline, low-Vt usage, and 50% keeper downsizing. Gate-source underdrive of -V cc on read-select transistors is established without additional supply/bias voltages or gate-oxide overstress. 8% faster read performance and 36% higher dc noise robustness is achieved compared to dual-Vt bitline scheme optimized for high performance. Device-level measurements in the 130-nm technology show 703× bitline active leakage reduction, enabling continued Vt scaling and robust bitline scalability beyond 130-nm generation. Sustained performance and robustness benefit of the pseudostatic technique against conventional dynamic bitline with keeper-upsizing is also presented
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