| 1. |
- Ahmad, Shakeel, 1977-, et al.
(författare)
-
ADC on-Chip Dynamic Test by PWM Technique
- 2008
-
Ingår i: International Conference on Signals and Electronic Systems. - : IEEE. ; , s. 15-18
-
Konferensbidrag (refereegranskat)abstract
- This paper investigates the feasibility of pulse width modulation technique (PWM) for dynamic test of ADCs used for high speed applications. The requirements and limitations of digital PWM signal to noise ratio (SNR) are discussed in terms of pulse-width resolution corresponding to the choice of the carrier- and clock frequency of a pulse-width generator. The PWM SNR response is measured by FFT using coherent sampling for different PWM resolution. Low-pas filtering removing high frequency PWM components is introduced as well to improve PWM SNR and prevent intermodulation effects, which tend to hamper the harmonic distortion test (HD). As an example a 4-bit first-order SigmaDelta ADC under dynamic test is simulated and the requirements for PWM resolution with respect to SNR and HD measurements are identified.
|
|
| 2. |
- Ahmad, Shakeel, 1977-, et al.
(författare)
-
Cancellation of Spurious Spectral Components in One-Bit Stimuli Generator
- 2010
-
Ingår i: Proceedings of IEEEInternational Conference on Signals and Electronic Systems, (ICSES 10). - : IEEE. - 9781424453078 ; , s. 393-396
-
Konferensbidrag (refereegranskat)abstract
- This work presents a cancellation technique of non-linear distortion components of one-bit digital stimulus sequence which is generated in software by a ΣΔ modulator. The stimulus is stored in a cyclic memory and applied to a circuit under test through a driving buffer and a simple lowpass reconstruction filter. The distortion components originate from buffer imperfections which result in a possible asymmetry between rising and falling edges of a NRTZ waveform representing the encoded stimulus. We show that the distortion components can be cancelled by using a simple predistortion technique. In addition an on-chip DC-calibrated ADC can be used to identify the second-order nonlinear products of the driving buffer. This procedure allows for cancellation of all the second-order distortions before the actual test and it can be extended to the third order terms as well.
|
|
| 3. |
|
|
| 4. |
- Ahmad, Shakeel, 1977-, et al.
(författare)
-
On-chip Stimuli Generation for ADC Dynamic Test by ΣΔ Technique
- 2009
-
Ingår i: Proceedings in European Conference on Circuit Theory and Design 2009 (ECCTD´09), Antalya, Turkey. - : IEEE. - 9781424438969 ; , s. 105-108
-
Konferensbidrag (refereegranskat)abstract
- This paper presents application of the ΣΔ modulation technique to the on-chip dynamic test for A/D converters. The wanted stimulus such as a single- or two-tone signal is encoded into one-bit ΣΔ sequence, which after simple low-pass filtering is applied to the circuit under test with low noise and without distortion. In this way a large dynamic range is achieved making the performance harmonic- and intermodulation dynamic test viable. By a systematic approach we select the order and type of a ΣΔ modulator, and develop the frequency plan suitable for spectral measurements on a chip. The technique is illustrated by simulation of a practical ADC under test.
|
|
| 5. |
|
|
| 6. |
- Ahmad, Shakeel, 1977-, et al.
(författare)
-
Two-tone PLL for on-chip IP3 test
- 2010
-
Ingår i: Proceedings of IEEEInternational Symposium on Circuits and Systems, (ISCAS 10). - : IEEE. - 9781424453085 ; , s. 3549-3552
-
Konferensbidrag (refereegranskat)abstract
- This paper addresses a built-in-self-test (BiST) to characterize IP3 linearity of a RF receiver front-end. A two-tone stimulus is generated by a phase-lock loop (PLL) in GHz frequency range. The PLL is designed to keep the frequency difference between the two tones under control and in this way to avoid a possible injection-locking. One of the oscillation frequencies and the difference (beat) frequency can be externally controlled. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the VCO and analog adder design. A highly linear analog adder with output referred IP3 of more than +15 dBm is used to generate the RF stimulus. The two-tone power across 50 Ω receiver input impedance can be more than -25 dBm with very low intermodulation distortion of PIM3 = -75 dBc. The receiver performance is not affected significantly by the test set-up. Simulations for linearity and noise performance of the PLL designed in 65nm CMOS show sufficient potential for on-chip IP3 measurements in the GHz frequency range.
|
|
| 7. |
|
|
| 8. |
|
|
| 9. |
|
|
| 10. |
|
|
