| 1. |
- Wang, C. H., et al.
(författare)
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High-k dielectrics on (100) and (110) n-InAs: Physical and electrical characterizations
- 2014
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Ingår i: AIP Advances. - : AIP Publishing. - 2158-3226. ; 4:4
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Tidskriftsartikel (refereegranskat)abstract
- Two high-k dielectric materials (Al2O3 and HfO2) were deposited on n-type (100) and (110) InAs surface orientations to investigate physical properties of the oxide/semiconductor interfaces and the interface trap density (D-it). X-ray photoelectron spectroscopy analyses (XPS) for native oxides of (100) and (110) as-grown n-InAs epi wafers show an increase in As-oxide on the (100) surface and an increase in InOx on the (110) surface. In addition, XPS analyses of high-k (Al2O3 and HfO2) on n-InAs epi show that the intrinsic native oxide difference between (100) and (110) epi surfaces were eliminated by applying conventional in-situ pre-treatment (TriMethyAluminium (TMA)) before the high-k deposition. The capacitance-voltage (C-V) characterization of HfO2 and Al2O3 MOSCAPs on both types of n-InAs surfaces shows very similar C-V curves. The interface trap density (D-it) profiles show D-it minima of 6.1 x 10(12/)6.5 x 10(12) and 6.6 x 10(12)/7.3 x 10(12) cm(-2) eV(-1) for Al2O3 and HfO2, respectively for (100) and (110) InAs surfaces. The similar interface trap density (D-it) on (100) and (110) surface orientation were observed, which is beneficial to future InAs FinFET device with both (100) and (110) surface channel orientations present. (C) 2014 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution 3.0 Unported License.
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| 2. |
- Wang, C. H., et al.
(författare)
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InAs hole inversion and bandgap interface state density of 2 x 10(11) cm(-2) eV(-1) at HfO2/InAs interfaces
- 2013
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Ingår i: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 103:14
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Tidskriftsartikel (refereegranskat)abstract
- High-k/InAs interfaces have been manufactured using InAs surface oxygen termination and low temperature atomic layer deposition of HfO2. Capacitance-voltage (C-V) curves revert to essentially classical shape revealing mobile carrier response in accumulation and depletion, hole inversion is observed, and predicted minority carrier response frequency in the hundred kHz range is experimentally confirmed; reference samples using conventional techniques show a trap dominated capacitance response. C-V curves have been fitted using advanced models including nonparabolicity and Fermi-Dirac distribution. For an equivalent oxide thickness of 1.3 nm, an interface state density D-it = 2.2 x 10(11) cm(-2) eV(-1) has been obtained throughout the InAs bandgap. (C) 2013 AIP Publishing LLC.
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| 3. |
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| 4. |
- Vasen, T., et al.
(författare)
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InAs nanowire GAA n-MOSFETs with 12-15 nm diameter
- 2016
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Ingår i: 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. - 9781509006373 ; 2016-September
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Konferensbidrag (refereegranskat)abstract
- InAs nanowires (NW) grown by MOCVD with diameter d as small as 10 nm and gate-All-Around (GAA) MOSFETs with d = 12-15 nm are demonstrated. Ion = 314 μA/μm, and Ssat =68 mV/dec was achieved at Vdd = 0.5 V (Ioff = 0.1 μA/μm). Highest gm measured is 2693 μS/μm. Device performance is enabled by small diameter and optimized high-k/InAs gate stack process. Device performance tradeoffs between gm, Ron, and Imin are discussed.
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| 5. |
- Passlack, M., et al.
(författare)
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Core-shell tfet developments and tfet limitations
- 2019
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Ingår i: 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. - 9781728109428
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Konferensbidrag (refereegranskat)abstract
- Tunneling field-effect transistors (TFET) based on a vertical gate-All-Around (VGAA) nanowire (NW) architecture with a core-shell (CS) structure have been explored for future CMOS applications. Performance predictions based on a tight-binding mode-space NEGF technique include a drive current \mathrm{I}-{\mathrm{o}\mathrm{n}} of 6.7\ \mu \mathrm{A} (NW diameter \mathrm{d}= 10.2\ \mathrm{nm}) at \mathrm{V}-{\mathrm{dd}}=0.3\ \mathrm{V} under low power (LP) conditions (\mathrm{I}-{\mathrm{off}}=1 \mathrm{pA}) for an InAs/GaSb CS TFET. This compares to Si nMOSFET \mathrm{I}-{\mathrm{on}} =2.3\ \mu \mathrm{A} at \mathrm{V}-{\mathrm{dd}}=0.55\ \mathrm{V}(\mathrm{d}=6\ \mathrm{nm}). On the experimental side, scaling of vertical CS NWs resulted in smallest dimensions of \mathrm{d}-{\mathrm{c}}= 17 nm (GaSb core) and \mathrm{t}-{\mathrm{sh}}=3 nm (InAs shell) for a total diameter of 23 nm. VGAA CS nFETs demonstrated drive current of up to 40\ \mu \mathrm{A} (\mathrm{V}-{\mathrm{d}}=0.3\ \mathrm{V}) and subthreshold swing \mathrm{SS}=40\mathrm{mV}/\mathrm{dec}(\mathrm{V}-{\mathrm{d}}=10\mathrm{mV}) for NW diameters between 35-50 nm. Although key TFET properties such as current drive and subthermal SS have been demonstrated using a VGAA CS architecture for the first time, experimental results still lag predictions. An intrinsic relationship between band-To band-Tunneling (BTBT) and \mathrm{D}-{\mathrm{it}} related trap assisted tunneling (TAT) was found which imposes challenging \mathrm{D}-{\mathrm{it}} requirements, in particular for LP \mathrm{I}-{\mathrm{off}} specifications. Complexity of fabrication and a material system foreign to CMOS manufacturing further impact prospects of TFET technology.
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| 6. |
- Vasen, T., et al.
(författare)
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Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs
- 2019
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Ingår i: Scientific Reports. - : Springer Science and Business Media LLC. - 2045-2322. ; 9:1
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Tidskriftsartikel (refereegranskat)abstract
- Tunneling Field-Effect Transistors (TFET) are one of the most promising candidates for future low-power CMOS applications including mobile and Internet of Things (IoT) products. A vertical gate-all-around (VGAA) architecture with a core shell (C-S) structure is the leading contender to meet CMOS footprint requirements while simultaneously delivering high current drive for high performance specifications and subthreshold swing below the Boltzmann limit for low power operation. In this work, VGAA nanowire GaSb/InAs C-S TFETs are demonstrated experimentally for the first time with key device properties of subthreshold swing S = 40 mV/dec (Vd = 10 mV) and current drive up to 40 μA/wire (Vd = 0.3 V, diameter d = 50 nm) while dimensions including core diameter d, shell thickness and gate length are scaled towards CMOS requirements. The experimental data in conjunction with TCAD modeling reveal interface trap density requirements to reach industry standard off-current specifications.
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