| 1. |
- Di, Wu, 1979-, et al.
(författare)
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System Architecture for 3GPP LTE Modem Using a Programmable Baseband Processo
- 2009
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Ingår i: International Symposium on System-on-Chip (SoC 2009).
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Konferensbidrag (refereegranskat)abstract
- 3G evolution towards HSPA and LTE is ongoing which will substantially increase the throughput with higher spectral efficiency. This paper presents the system architecture of an LTE modem based on a programmable baseband processor. The architecture includes a baseband processor that handles processing such as time and frequency synchronization, IFFT/FFT (up to 2048-p), channel estimation and subcarrier demapping. The throughput and latency requirements of a Category 4 User Equipment (CAT4 UE) is met by adding a MIMO symbol detector and a parallel Turbo decoder supporting H-ARQ. This brings both low silicon cost and enough flexibility to support other wireless standards. The complexity demonstrated by the modem shows the practicality and advantage of using programmable baseband processors for a single-chip LTE solution.
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| 2. |
- Asghar, Rizwan, 1973-, et al.
(författare)
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Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding
- 2010
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Ingår i: Journal of Signal Processing Systems for Signal, Image, and Video Technology. - : Springer Science and Business Media LLC. - 1939-8018. ; 60:1, s. 15-29
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a novel hardware interleaver architecture for unified parallel turbo decoding. The architecture is fully re-configurable among multiple standards like HSPA Evolution, DVB-SH, 3GPP-LTE and WiMAX. Turbo codes being widely used for error correction in today’s consumer electronics are prone to introduce higher latency due to bigger block sizes and multiple iterations. Many parallel turbo decoding architectures have recently been proposed to enhance the channel throughput but the interleaving algorithms used indifferent standards do not freely allow using them due to higher percentage of memory conflicts. The architecture presented in this paper provides a re-configurable platform for implementing the parallel interleavers for different standards by managing the conflicts involved in each. The memory conflicts are managed by applying different approaches like stream misalignment, memory division and use of small FIFO buffer. The proposed flexible architecture is low cost and consumes 0.085 mm2 area in 65nm CMOS process. It can implement up to 8 parallel interleavers and can operate at a frequency of 200 MHz, thus providing significant support to higher throughput systems based on parallel SISO processors.
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| 3. |
- Asghar, Rizwan, 1974-, et al.
(författare)
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Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution
- 2009
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Ingår i: 12th EUROMICRO Conference on Digital System Design. - 9780769537825 ; , s. 699-706
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Konferensbidrag (refereegranskat)abstract
- HSPA evolution has raised the throughput requirements for WCDMA based systems where turbo code has been adapted to perform the error correction. Many parallel turbo decoding architectures have recently been proposed to enhance the channel throughput but the interleaving algorithm used in WCDMA based systems does not freely allows to use them due to high percentage of memory conflicts. This paper provides a comprehensive analysis for reduction of interleaver memory conflicts while generating more than one address in a single clock cycle. It also provides trade-off analysis in terms of area and power efficiency for multiple architectures for different functions involved in the interleaver design. The final architecture supports processing of two parallel SISO blocks and manages the conflicts by applying different approaches like stream misalignment, memory division and small FIFO buffer. The proposed architecture is low cost and consumes 4.3K gates at a frequency of 150MHz. This work also focuses on reduction of pre-processing overheads by introducing the segment based modulo computation, thus providing further relaxation to SISO decoding process.
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| 4. |
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| 5. |
- Eilert, Johan, 1980-, et al.
(författare)
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Complexity Reduction of Matrix Manipulation for Multi-User STBC-MIMO Decoding
- 2007
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Ingår i: IEEE Sarnoff Symmposium,2007. - 9781424424832 ; , s. 1-5
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Konferensbidrag (refereegranskat)abstract
- This paper studies efficient complex valued matrix manipulations for multi-user STBC-MIMO decoding. A novel method called Alamouti blockwise analytical matrix inversion (ABAMI) is proposed for the inversion of large complex matrices that are based on Alamouti sub-blocks. Another method using a variant of Givens rotation is proposed for fast QR decomposition of this kind of matrices. Our solutions significantly reduce the number of operations which makes them more than 4 times faster than several other solutions in the literature. Furthermore, compared to fixed function VLSI implementations, our solution is more flexible and consumes less silicon area because the hardware is programmable and it can be reused for many other operations such as filtering, correlation and FFT/IFFT. Besides the analysis of the general computational complexity based on the number of basic operations, the computational latency is also measured in clock cycles based on the conceptual hardware for real-time matrix manipulations.
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| 6. |
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| 7. |
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| 8. |
- Eilert, Johan, 1980-, et al.
(författare)
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Efficient Complex Matrix Inversion for MIMO Software Defined Radio
- 2007
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Ingår i: International Symposium on Circuits and Systems, ISCAS,2007. - : IEEE. - 1424409209 ; , s. 2610-2613
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Konferensbidrag (refereegranskat)abstract
- Complex matrix inversion is a very computationally demanding operation in advanced multi-antenna wireless communications. Traditionally, systolic array-based QR decomposition (QRD) is used to invert large matrices. However, the matrices involved in MIMO baseband processing in mobile handsets are generally small which means QRD is not necessarily efficient. In this paper, a new method is proposed using programmable hardware units which not only achieves higher performance but also consumes less silicon area. Furthermore, the hardware can be reused for many other operations such as complex matrix multiplication, filtering, correlation and FFT/IFFT.
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| 9. |
- Eilert, Johan, 1980-, et al.
(författare)
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Implementation of a Programmable Linear MMSE Detector for MIMO-OFDM
- 2008
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Ingår i: IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP,2008. - : IEEE. - 9781424414833 ; , s. 5396-5399
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Konferensbidrag (refereegranskat)abstract
- This paper presents a linear minimum mean square error (LMMSE) symbol detector for MIMO-OFDM enabled mobile terminals. The detector is implemented using a programmable baseband processor aimed for software-defined radio (SDR). Owing to the dynamic range supplied by the floating-point SIMD datapath, special algorithms can be adopted to reduce the computational latency of detection. The programmable solution not only supports different transmit/receive antenna configurations, but also allows hardware multiplexing to obtain silicon and power efficiency. Compared to several existing fixed-functional solutions, the one proposed in this paper is smaller, more flexible and faster.
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| 10. |
- Eilert, Johan, 1980-, et al.
(författare)
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Real-Time Alamouti STBC Decoding on A Programmable Baseband Processor
- 2008
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Konferensbidrag (refereegranskat)abstract
- This paper presents a space-time block coding decoder for MIMO-OFDM enabled mobile terminals. The decoder is implemented using a programmable baseband processor aimed for software-defined radio (SDR). The dynamic range supplied by the floating-point SIMD datapath allows special algorithms to significantly reduce the computational latency of decoding. The programmable solution not only supports different transmit/receive antenna configuration, but also allows hardware multiplexing to obtain silicon and power efficiency. Compared to several existing fixed-functional ASIC solutions in literature, the one proposed in this paper is by far the smallest, fastest and with more flexibility.
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