| 1. |
- El Ghany, M. A. A., et al.
(författare)
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High throughput high performance NoC switch
- 2008
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Konferensbidrag (refereegranskat)abstract
- Increasing the number of virtual channels can improve the throughput in an on-chip interconnection network. High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch.
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| 2. |
- Abd El Ghany, M. A., et al.
(författare)
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Asynchronous BFT for low power networks on chip
- 2010
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Ingår i: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems. - : IEEE. - 9781424453092 ; , s. 3240-3243
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Konferensbidrag (refereegranskat)abstract
- Asynchronous Butterfly Fat Tree (BFT) architecture is proposed to achieve low power Network on Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches (αdata satisfies a certain condition. The area of Asynchronous BFT switch is increased by 25% as compared to Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by up to 33% as compared to the power dissipation of the conventional Synchronous architecture when the αdata equals 0.2 and the activity factor of the control signals is equal to 1/64 of the αdata. The total metal resources required to implement Asynchronous design is decreased by 12%.
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| 3. |
- Abd El Ghany, M. A., et al.
(författare)
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High throughput architecture for CLICHÉ network on chip
- 2009
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Ingår i: Proceedings - IEEE International SOC Conference, SOCC 2009. - 9781424452200 ; , s. 155-158
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Konferensbidrag (refereegranskat)abstract
- High Throughput Chip-Level Integration of Communicating Heterogeneous Elements (CLICHÉ) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 40% while preserving the average latency. The area of High Throughput CLICHÉ switch is decreased by 18% as compared to CLICHÉ switch. The total metal resources required to implement High Throughput CLICHÉ design is increased by 7% as compared to the total metal resources required to implement CLICHÉ design. The extra power consumption required to achieve the proposed architecture is 8% of the total power consumption of the CLICHÉ architecture.
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| 4. |
- Abd El Ghany, M. A., et al.
(författare)
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High throughput architecture for high performance NoC
- 2009
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Ingår i: ISCAS. - : IEEE. - 9781424438280 ; , s. 2241-2244
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Konferensbidrag (refereegranskat)abstract
- High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption required to achieve the proposed architecture is 3% of the total power consumption of the BFT architecture.
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| 5. |
- Abd El Ghany, M. A., et al.
(författare)
-
Power characteristics of networks on chip
- 2010
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Ingår i: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems. - : IEEE. - 9781424453092 ; , s. 3721-3724
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Konferensbidrag (refereegranskat)abstract
- Power characteristics of different Network on Chip (NoC) topologies are developed. Among different NoC topologies, the Butterfly Fat Tree (BFT) dissipates the minimum power. With the advance in technology, the relative power consumption of the interconnects and the associate repeaters of the BFT decreases as compared to the power consumption of the network switches. The power dissipation of interswitch links and repeaters for BFT represents only 1% of the total power dissipation of the network. In addition of providing high throughput, the BFT is a power efficient topology for NoCs.
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| 6. |
- Abd El Ghany, M. A., et al.
(författare)
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Power efficient networks on chip
- 2009
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Ingår i: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009. - 9781424450916 ; , s. 105-108
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Konferensbidrag (refereegranskat)abstract
- a low power switch design is proposed to achieve power-efficient Network on Chip (NoC). The proposed NoC switch reduce. The power consumption oy the Butterfly Fat Tree (BFT) architecture by 28 % as compared to the conventional BFT switch. Moreover. The power reduction technique is applied to different NoC architectures. The technique reduce. The power consumption oy the network by up to 41%. Whe. The power consumption oy the whole network includin. The interswich links and repeaters is taken into account. The overall power consumption is decreased by up to 33% at the maximum operating frequency oy the switch. The BFT architecture consume. The minimum power as compared to other NoC architectures.
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| 7. |
- Abd Elghany, M. A., et al.
(författare)
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High throughput architecture for OCTAGON network on chip
- 2009
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Ingår i: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009. - : IEEE. - 9781424450916 ; , s. 101-104
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Konferensbidrag (refereegranskat)abstract
- High Throughput Octagon architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increase. The throughput oy the network by 17% while preservin. The average latency. The area of High Throughput OCTAGON switch is decreased by 18% as compared to OCTAGON switch. The total metal resources required to implement High Throughput OCTAGON design is increased by 8% as compared to the total metal resources required to implement OCTAGON design. The extra power consumption required to achiev. The proposed architecture is 2% oy the total power consumption oy the OCTAGON architecture.
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