| 1. |
- Elahipanah, Hossein, 1982-, et al.
(författare)
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500 °C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits
- 2017
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Ingår i: IEEE Electron Device Letters. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 0741-3106 .- 1558-0563.
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Tidskriftsartikel (refereegranskat)abstract
- High-current 4H-SiC lateral BJTs for high-temperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (JC), lower on-resistance (RON), and more uniform current distribution. A maximum current gain (β) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs are measured from room temperature to 500 °C. An open-base breakdown voltage (VCEO) of >50 V is measured for the devices.
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| 2. |
- Elahipanah, Hossein, 1982-, et al.
(författare)
-
A Wafer-Scale Self-Aligned Ni-Silicide (SALICIDE) Low-Ohmic Contact Technology on n-type 4H-SiC
- 2017
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Ingår i: ECS Journal of Solid State Science and Technology. - : ECS. - 2162-8769 .- 2162-8777. ; 6:4, s. 197-200
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Tidskriftsartikel (refereegranskat)abstract
- A self-aligned nickel (Ni) silicide process for n-type Ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5×10-6 Ω·cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale, which saves time and cost.
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| 3. |
- Elahipanah, Hossein, 1982-
(författare)
-
Design Optimization and Realization of 4H-SiC Bipolar Junction Transistors
- 2017
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- 4H-SiC-based bipolar junction transistors (BJTs) are attractive devices for high-voltage and high-temperature operations due to their high current capability, low specific on-resistance, and process simplicity. To extend the potential of SiC BJTs to power electronic industrial applications, it is essential to realize high-efficient devices with high-current and low-loss by a reliable and wafer-scale fabrication process. In this thesis, we focus on the improvement of the 4H-SiC BJT performance, including the device optimization and process development.To optimize the 4H-SiC BJT design, a comprehensive study in terms of cell geometries, device scaling, and device layout is performed. The hexagon-cell geometry shows 42% higher current density and 21% lower specific on-resistance at a given maximum current gain compared to the interdigitated finger design. Also, a layout design, called intertwined, is used for 100% usage of the conducting area. A higher current is achieved by saving the inactive portion of the conducting area. Different multi-step etched edge termination techniques with an efficiency of >92% are realized.Regarding the process development, an improved surface passivation is used to reduce the surface recombination and improve the maximum current gain of 4H-SiC BJTs. Moreover, wafer-scale lift-off-free processes for the n- and p-Ohmic contact technologies to 4H-SiC are successfully developed. Both Ohmic metal technologies are based on a self-aligned Ni-silicide (Ni-SALICIDE) process.Regarding the device characterization, a maximum current gain of 40, a specific on-resistance of 20 mΩ·cm2, and a maximum breakdown voltage of 5.85 kV for the 4H-SiC BJTs are measured. By employing the enhanced surface passivation, a maximum current gain of 139 and a specific on-resistance of 579 mΩ·cm2 at the current density of 89 A/cm2 for the 15-kV class BJTs are obtained. Moreover, low-voltage 4H-SiC lateral BJTs and Darlington pair with output current of 1−15 A for high-temperature operations up to 500 °C were fabricated.This thesis focuses on the improvement of the 4H-SiC BJT performance in terms of the device optimization and process development for high-voltage and high-temperature applications. The epilayer design and the device structure and topology are optimized to realize high-efficient BJTs. Also, wafer-scale fabrication process steps are developed to enable realization of high-current devices for the real applications.
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| 4. |
- Elahipanah, Hossein, 1982-, et al.
(författare)
-
Modification of Etched Junction Termination Extension for the High Voltage 4H-SiC Power Devices
- 2016
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Ingår i: Materials Science Forum. - : Trans Tech Publications Inc.. - 0255-5476 .- 1662-9752. ; 858, s. 978-981
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Tidskriftsartikel (populärvet., debatt m.m.)abstract
- High voltage 4H-SiC bipolar junction transistors (BJTs) with modified etched junction termination extension (JTE) are fabricated and optimized in terms of the length and remaining dose of JTEs. It is found that the JTE1 is the most effective one in spreading the electric field. Hence, for a given total termination length, a decremental JTE length from the innermost edge to the outermost mesa edge of the device results in better modification of the electric field. A breakdown voltage of 4.95 kV is measured for the modified device, which shows ~20% improvement of the termination efficiency for no extra cost or extra process step. Equal-size BJTs by interdigitated-emitter with different number of fingers and cell pitches are fabricated. It is presented that the maximum current gain decreases by having more fingers while the maximum current gain is achieved at higher current density.
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