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Sökning: WFRF:(Ellervee Peeter)

  • Resultat 1-10 av 52
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  • Cavo, Luis, et al. (författare)
  • Implementation of an area efficient crypto processor for a NB-IoT SoC platform
  • 2018
  • Ingår i: 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018 : NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings - NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings. - 9781538676561
  • Konferensbidrag (refereegranskat)abstract
    • This paper presents a cryptographic processor compliant with the security algorithms specified by the 3rd Generation Partnership Project (3GPP) specifications for Long Term Evolution (LTE). The proposed processor has been adapted to the needs of the low end portfolio technologies that compose the Internet of Things (IoT) market, which addresses low-Area, low-cost and low-data rate applications. The cryptographic processor has been described using the High-Level Synthesis (HLS) design flow and integrated with a CPU in a cycle accurate virtual platform. Various architectural optimizations are proposed in order to achieve a reduction of area ranging from 5% to 42% in comparison to similar work. In a 65-nm CMOS technology, the processor has a size of 53.6 kGE, and is capable of performing at 52.4 Mbps for the block cipher and 800 Mbps for the stream cipher algorithms at a 100 MHz clock.
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  • Ellervee, Peeter, et al. (författare)
  • Exploiting data transfer locality in memory mapping
  • 1999
  • Ingår i: EUROMICRO Conference, 1999. Proceedings. 25th. ; , s. 14-21
  • Konferensbidrag (refereegranskat)abstract
    • System-level exploration of memory architectures is one of the key issues in successful implementation of data-transfer dominated applications. Usually, one of the main design bottlenecks is the memory access bandwidth. Transformations, rearranging the layout of the data records stored in memory, are very effective to improve the locality of the data transfers but usually lead to a large memory bit-wastage when not performed carefully. In this paper, a methodology which reduces memory bandwidth requirements without sacrificing storage space is proposed. The methodology exploits parallelism in the data-transfers to rearrange the layout of the data records. Distributed memory organization combined with our proposed layout rearrangement methodology allow to effectively reduce the memory bandwidth bottleneck in data-transfer dominated applications
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  • Ellervee, Peeter, et al. (författare)
  • Exploring ASIC Design Space at System Level with a Neural Network Estimator
  • 1994
  • Ingår i: Proc. of IEEE ASIC-conference, 1994.
  • Konferensbidrag (refereegranskat)abstract
    • Estimators are critical tools in doing architectural level exploration of the design space. We present a novel approach to estimation based on the multilayer perceptron which builds the estimation function during the learning process and thus allows to describe arbitrary complex functions. We also describe how the control data flow graph is encoded for the neural network input and we present results of the first experiments made with realistic design examples.
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  • Resultat 1-10 av 52

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