1. |
- Collaert, N., et al.
(författare)
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Ultimate nano-electronics : New materials and device concepts for scaling nano-electronics beyond the Si roadmap
- 2015
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 132, s. 218-225
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Tidskriftsartikel (refereegranskat)abstract
- Abstract In this work, we will give an overview of the innovations in materials and new device concepts that will be needed to continue Moore’s law to the sub-10 nm technology nodes. To meet the power and performance requirements high mobility materials in combination with new device concepts like tunnel FETs and gate-all-around devices will need to be introduced. As the density is further increased and it becomes increasingly difficult to put contacts, spacers and gate in the available gate pitch, disruptive integration schemes such as vertical transistors and monolithic 3D integration might lead the way to the ultimate scaling of CMOS.
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2. |
- Eneman, K., et al.
(författare)
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Evaluation of signal enhancement algorithms for hearing instruments
- 2008
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Konferensbidrag (refereegranskat)abstract
- In the frame of the HearCom1 project five promising signal enhancement algorithms are validated for future use in hearing instrument devices. To assess the algorithm performance solely based on simulation experiments, a number of physical evaluation measures have been proposed that incorporate basic aspects of normal and impaired human hearing. Additionally, each of the algorithms has been implemented on a common real-time hardware/software platform, which facilitates a profound subjective validation of the algorithm performance. Recently, a multicenter study has been set up across five different test centers in Belgium, the Netherlands, Germany and Switzerland to perceptually evaluate the selected signal enhancement approaches with normally hearing and hearing impaired listeners.
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3. |
- O'Neill, A., et al.
(författare)
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Reduced self-heating by strained silicon substrate engineering
- 2008
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Ingår i: Applied Surface Science. - : Elsevier BV. - 0169-4332 .- 1873-5584. ; 254:19, s. 6182-6185
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Tidskriftsartikel (refereegranskat)abstract
- Substrate engineering innovations such as SOI and the use of Si/SiGe virtual substrates become necessary in order to maintain performance leverage of integrated circuits with continued scaling. The relevance of thermal effects in device design increases since the thermal conductivity of these new materials is poor. The electrical performance of devices fabricated on thin virtual substrates grown by two different techniques is presented. It is found that self-heating is reduced and that thermal resistance measurements agree with modelling predictions. The reduction in performance enhancement seen in many strained Si MOSFETs is found here to be largely due to self-heating effects, rather than parasitics or the loss of strain.
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