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Sökning: WFRF:(Fanori Luca)

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1.
  • Fanori, Luca, et al. (författare)
  • A 2.4-to-5.3GHz Dual-Core CMOS VCO with Concentric 8-Shaped Coils
  • 2014
  • Ingår i: 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). - 0193-6530. - 9781479909186 ; 57, s. 370-370
  • Konferensbidrag (refereegranskat)abstract
    • Despite recent attempts to relax the phase-noise demands on voltage-controlled oscillators (VCOs) for cellular communications [1], mainstream radios require harmonic VCOs capable of a very low phase noise with moderate power consumption, associated to a large tuning range (TR) and a high insensitivity to interfering signals. Ideally, the TR should be in excess of one octave, since this allows the easy synthesis of all frequencies below those directly generated by the VCOs via repeated frequency divisions by 2. At the same time, the oscillation spectrum should be affected as little as possible by spurious (common-mode) magnetic fields impinging on the inductor coil in the VCO tank. This is a crucial requirement in modern radios, where there are more PLLs active at the same time, and particularly when (non-contiguous) carrier aggregation is implemented, since in this case the signal bands may be very close to each other. If an individual PLL is used for each band, the VCOs may oscillate very close to each other, or at frequencies that are harmonically related to each other, posing a very serious issue of mutual pulling through the respective magnetic field. And even if a single VCO is used [2], or two (or more) VCOs that are not harmonically related [3], it is nevertheless a good practice to design the tank inductor as insensitive as possible to external magnetic fields, which abound in and close to the radio IC.
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2.
  • Fanori, Luca, et al. (författare)
  • A 2.8-to-5.8 GHz harmonic VCO in a 28 nm UTBB FD-SOI CMOS process
  • 2015
  • Ingår i: 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). - 9781479976423 ; , s. 195-198
  • Konferensbidrag (refereegranskat)abstract
    • A 2.8-to-5.8GHz VCO designed in a 28nm UTBB FD-SOI CMOS process adopts a reconfigurable active core to save power at the lower oscillation frequencies, and to enable a trade-off between power consumption and phase noise at all frequencies. The UTBB FD-SOI CMOS process is instrumental to achieve a tuning range in excess of one octave at low power consumption, while the use of an 8-shaped tank coil yields a VCO that is highly insensitive to external magnetic fields. The VCO operates from 0.9V and has a figure-of-merit of 186-189 dBc/Hz, depending on the oscillation frequency and the configuration of the oscillator core. The active area of the VCO is 380 μm × 700 μm.
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3.
  • Fanori, Luca, et al. (författare)
  • A Class-D CMOS DCO with an on-chip LDO
  • 2014
  • Ingår i: Proceedings Of The 40th European Solid-State Circuit Conference (ESSCIRC 2014). - 1930-8833. ; , s. 335-338
  • Konferensbidrag (refereegranskat)abstract
    • This paper presents the co-design of a class-D digitally-controlled oscillator (DCO) and a low-dropout voltage regulator (LDO) generating the supply voltage for the DCO. Despite the high intrinsic supply pushing of the class-D oscillator topology, the LDO noise has only a very marginal impact on the DCO phase noise. The class-D DCO and LDO have been integrated in a 65nm CMOS process without any thick top metal layer. The oscillation frequency is tunable between 3.0 GHz and 4.3 GHz, for a tuning range of 36%, with a fine frequency step below 3 kHz and a fine frequency range of 10MHz (both measured at 3 GHz). Drawing 9.0mA from 0.4V (corresponding to an unregulated supply voltage of 0.6 V), the phase noise is -145.5 dBc/Hz at a 10MHz offset from a 3.0 GHz carrier. The resulting FoM is 189.5 dBc/Hz, and varies less than 1 dB across the tuning range. The FoM increases to above 190 dBc/Hz when the regulated supply voltage is 0.5V.
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4.
  • Fanori, Luca, et al. (författare)
  • Class-D CMOS Oscillators
  • 2013
  • Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200. ; 48:12, s. 3105-3119
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper presents class-D CMOS oscillators capable of an excellent phase noise performance from a very low power supply voltage. Starting from the recognition of the time-variant nature of the class-D LC tank, accurate expressions of the oscillation frequency, oscillation amplitude, current consumption, phase noise, and figure-of-merit (FoM) have been derived. Compared with the commonly used class-B/C architectures, the optimal class-D oscillator produces less phase noise for the same power consumption, at the expense of a higher power supply pushing. A prototype of a class-D voltage-controlled oscillator (VCO) targeted for mobile applications, implemented in a standard 65-nm CMOS process, covers a 46% tuning range between 3.0 and 4.8 GHz; drawing 10 mA from 0.4 V, the phase noise at 10-MHz offset from 4.8 GHz is -143.5 dBc/Hz, for an FoM of 191 dBc/Hz with less than 1-dB variation across the tuning range. A version of the same VCO with a resonant tail filter displays a lower 1/f(3) phase-noise corner and improves the FoM by 1 dB.
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5.
  • Fanori, Luca, et al. (författare)
  • Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs
  • 2013
  • Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200. ; 48:7, s. 1730-1740
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper presents two class-C CMOS VCOs with a dynamic bias of the core transistors, which maximizes the oscillation amplitude without compromising the robustness of the oscillation start-up, thereby breaking the most severe trade-off in the original class-C topology. An analysis of several different oscillators, starting with the common class-B architecture and arriving to the proposed class-C design, shows that the latter exhibits a figure-of-merit (FoM) that is closest to the ideal FoM allowed by the integration technology. The class-C VCOs have been implemented in a 90 nm CMOS process with a thick top metal layer. They are tunable between 3.4 GHz and 4.5 GHz, covering a tuning range of 28%. Drawing 5.5 mA from 1.2 V, the phase noise is lower than -152 dBc/Hz at a 20 MHz offset from a 4 GHz carrier. The resulting FoM is 191 dBc/Hz, and varies less than 1 dB across the tuning range.
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6.
  • Liscidini, Antonio, et al. (författare)
  • A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers
  • 2014
  • Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200. ; 49:3, s. 646-656
  • Tidskriftsartikel (refereegranskat)abstract
    • A Digitally Controlled Oscillator (DCO) whose power consumption can be reconfigured while maintaining an almost constant phase-noise figure-of-merit (FoM). This is achieved by using either a single-switch-pair or a complementary (i.e., double-switch-pair) oscillator topology, without disturbing the optimized LC tank of the DCO. The optimal power consumption in the complementary (P-N) configuration is reduced by 75% compared to the single-switch-pair (N-only) configuration, while the FoM is kept constant. Measurements on a 55 nm CMOS 4 GHz DCO prototype show a minimum phase noise of -129.3 dBc/Hz at 2 MHz offset from the carrier in the P-N configuration, and of -134.7 dBc/Hz in the N-only configuration, with a phase noise difference very close to the 6 dB expected from theory. The current consumption is 6 mA and 24 mA, respectively, resulting in approximately the same FoM of -185 dBc/Hz.
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7.
  • Mahmoud, Ahmed, et al. (författare)
  • A 2.8-to-5.8 GHz harmonic VCO based on an 8-shaped inductor in a 28 nm UTBB FD-SOI CMOS process
  • 2016
  • Ingår i: Analog Integrated Circuits and Signal Processing. - : Springer Science and Business Media LLC. - 0925-1030 .- 1573-1979. ; 88:3, s. 391-399
  • Tidskriftsartikel (refereegranskat)abstract
    • A 2.8-to-5.8 GHz harmonic VCO designed in a 28 nm UTBB FD-SOI CMOS process adopts a reconfigurable active core to save power at the lower oscillation frequencies, and to enable a trade-off between power consumption and phase noise at all frequencies. Interference caused by the magnetic coupling to and from the VCO inductor is greatly attenuated by resorting to an inductor in the shape of an 8. Simulations of the magnetic coupling between an 8-shaped inductor and a reference inductor show a reduction in magnetic coupling as high as 44 dB, depending also on size, orientation, and shape of the reference inductor. The UTBB FD-SOI CMOS process is instrumental to achieve a tuning range in excess of one octave at low power consumption. The VCO operates from 0.9 V and has a figure-of-merit of 186–189 dBc/Hz, depending on the oscillation frequency and the configuration of the oscillator core. The active area of the VCO is 380 × 700 µm.
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  • Resultat 1-7 av 7
Typ av publikation
tidskriftsartikel (4)
konferensbidrag (3)
Typ av innehåll
refereegranskat (7)
Författare/redaktör
Fanori, Luca (7)
Andreani, Pietro (5)
Mattsson, Thomas (4)
Caputa, Peter (2)
Mahmoud, Ahmed (2)
Andreani, Piero (2)
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Rämö, Sami (1)
Liscidini, Antonio (1)
Castello, Rinaldo (1)
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Lunds universitet (7)
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