| 1. |
- Salahvarzi, Arash, et al.
(författare)
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WiSE : When Learning Assists Resolving STT-MRAM Efficiency Challenges
- 2023
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Ingår i: IEEE Transactions on Emerging Topics in Computing. - Piscataway, NJ : IEEE. - 2168-6750. ; 11:1, s. 43-55
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Tidskriftsartikel (refereegranskat)abstract
- Spin Transfer Torque Magnetic RAM (STT-MRAM) is one of the most promising on-chip technologies, which delivers high density, non-volatility, and near-zero leakage power. However, STT-MRAM suffers from three reliability issues, namely, read disturbance, write failure, and retention failure, that present significant challenges to its use as a reliable on-chip memory. All of these three reliability challenges become even more threatening with any increase in STT-MRAM cell temperature. Write operations are regarded as the main source of heat generation and temperature increase in STT-MRAM on-chip memories. This paper first presents experiments to show how the heat generated by consecutive writes affects the reliability of an STT-MRAM on-chip cache. Then, it proposes the WiSE framework, an approach to reduce the STT-MRAM-based cache memory temperature and improve its reliability. WiSE utilizes the Reinforcement Learning (RL) technique to detect high-density write operation patterns in STT-MRAM cache. To manage the write operations across the STT-MRAM caches, WiSE introduces a new temperature-aware replacement policy. The simulation results show that while WiSE imposes only about 1% performance overhead, it improves retention failure rate, read disturbance rate and write failure rate by 64%, 57%, and 47%, respectively, compared to Least Recently Used (LRU) replacement policy. (c) IEEE
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| 2. |
- Akbari, Maryam, et al.
(författare)
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An Ultra-compact Pure Magnetic Arbiter PUF with High Reliability and Low Power Consumption
- 2023
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Ingår i: IEEE transactions on nanotechnology. - Piscataway, NJ : Institute of Electrical and Electronics Engineers (IEEE). - 1536-125X .- 1941-0085. ; 22, s. 449-456
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Tidskriftsartikel (refereegranskat)abstract
- Due to the rugged environmental factors in IoT applications and constrained on-chip resources, PUF, as a critical hardware primitive, is a promising solution for key storage, authentication, and ID generation. The existing CMOS-based Arbiter PUFs mainly suffer from low reliability and vulnerability against modeling attacks. In this paper, the proposed PUF utilizes mCell devices, a class of Magnetoresistive devices employing only Magnetic Tunnel Junction (MTJ) devices, as a building block. Also, a novel nonvolatile latch is proposed to act as an arbiter and generates the responses by comparing the current values instead of delays which leads to increased the reliability by subtracting the constant variation rates of MTJs under environmental variation without adding hardware overhead. The characteristics of MTJ like nonvolatility, stochastic switching, chaotic magnetization, low power consumption, and low occupied area have made the proposed PUF to a low power, highly reliable, high randomness and ultra-compact pure magnetic arbiter PUF. The Monte Carlo HSPICE simulation results reveal that the uniformity, uniqueness, bit-aliasing, power consumption, and area of the proposed PUF are 49.24 %, 49.87 %, 48.64 %, 10.771 μW and 0.106 μm2, respectively. In addition, the average BER across a wide temperature range (-50∘ C 150∘ C) and voltage range (0.05 V-0.1 V) is 0.08 % and 0.18 %, respectively. © IEEE
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| 3. |
- Akbari, Maryam, et al.
(författare)
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Pure Magnetic Memory-Based PUFs : A Secure and Lightweight Solution for IoT Devices
- 2023
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Ingår i: Iranian Journal of Electrical and Electronic Engineering. - Tehran : Iran University of Science and Technology. - 2383-3890 .- 1735-2827. ; 19:4
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Tidskriftsartikel (refereegranskat)abstract
- In light of the growing prevalence of Internet of Things (IoT) devices, it has become essential to incorporate cryptographic protection techniques for high-security applications. Since IoT devices are resource-constraints in terms of power and area, finding cost-effective ways to enhance their security is necessary. Physical unclonable function (PUF) is considered a trusted hardware security mechanism that generates true and intrinsic randomness by extracting the inherent process variations of circuits. In this paper, a novel pure magnetic memory-based PUF is presented. The fundamental building blocks of the proposed PUF design are magnetic devices, the so-called mCells. These magnetoresistive devices exclusively utilize Magnetic Tunnel Junction (MTJ) components. Using purely MTJ in the main memory and sense amplifier in the proposed PUF leads to high randomness, high reliability, low power, and ultra-compact occupation area. The Monte Carlo HSPICE simulation results demonstrate that the proposed PUF achieves a uniqueness of 49.89%, uniformity of 50.02 %, power consumption of 1.43 µW, and an area occupation of 0.01 µm2 per bit. © 2023, Iran University of Science and Technology. All rights reserved.
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| 4. |
- Amininasab, Mehdi, et al.
(författare)
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SingAll : Scalable Control Flow Checking for Multi-Process Embedded Systems
- 2023
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Ingår i: 2023 13th International Conference on Computer and Knowledge Engineering (ICCKE). - : IEEE. - 9798350330151 - 9798350330168 ; , s. 42-47
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Konferensbidrag (refereegranskat)abstract
- Reliability concerns of embedded systems are traditionally resolved by software-based control flow checking (CFC) methods where the execution flow of the processor is monitored to detect and compensate flow violations. Traditional CFC methods may lose their efficiency when it comes to multiprocessing embedded systems. In this paper, we introduce and validate a novel flow error model for multiprocessing embedded systems. Further, we propose a holistic CFC system which performs the flow checking of the processes of interest. The proposed CFC checking introduces the concept of a single monitoring process intended to check the execution flow of as many processes as wanted within an multiprocessing embedded system. Proposed solution does not introduce any substantial overheads in performance and memory consumption. Even more important is method's insensitivity to the number of checked processes. Our wide evaluations show the average performance overhead of 13.77%, average code-size overhead of 51.71%, and the average memory overhead of 1.95% on the Mibench benchmark suite. Results of fault injections confirm that the proposed CFC method successfully detects more than 95% of flow errors including our newly defined error model. © 2023 IEEE.
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| 5. |
- Beitollahi, Hakem, et al.
(författare)
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Application Layer DDoS Attack Detection Using Cuckoo Search Algorithm-Trained Radial Basis Function
- 2022
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Ingår i: IEEE Access. - Piscataway, NJ : IEEE. - 2169-3536. ; 10, s. 63844-63854
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Tidskriftsartikel (refereegranskat)abstract
- In an application-layer distributed denial of service (App-DDoS) attack, zombie computers bring down the victim server with valid requests. Intrusion detection systems (IDS) cannot identify these requests since they have legal forms of standard TCP connections. Researchers have suggested several techniques for detecting App-DDoS traffic. There is, however, no clear distinction between legitimate and attack traffic. In this paper, we go a step further and propose a Machine Learning (ML) solution by combining the Radial Basis Function (RBF) neural network with the cuckoo search algorithm to detect App-DDoS traffic. We begin by collecting training data and cleaning them, then applying data normalizing and finding an optimal subset of features using the Genetic Algorithm (GA). Next, an RBF neural network is trained by the optimal subset of features and the optimizer algorithm of cuckoo search. Finally, we compare our proposed technique to the well-known k-nearest neighbor (k-NN), Bootstrap Aggregation (Bagging), Support Vector Machine (SVM), Multi-layer Perceptron) MLP, and (Recurrent Neural Network) RNN methods. Our technique outperforms previous standard and well-known ML techniques as it has the lowest error rate according to error metrics. Moreover, according to standard performance metrics, the results of the experiments demonstrate that our proposed technique detects App-DDoS traffic more accurately than previous techniques. © 2013 IEEE.
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| 6. |
- Esmaeilian, Maryam, et al.
(författare)
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Experimental Evaluation of Delayed-Based Detectors Against Power-off Attack
- 2023
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Ingår i: 2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS). - : IEEE. - 9798350341355 - 9798350341362
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Konferensbidrag (refereegranskat)abstract
- Embedded systems are vulnerable to significant security threats from Fault Injection Attacks (FIAs), which allow attackers to gain access to confidential information. While various attack detectors have been proposed in the literature to detect different types of FIAs, these detectors themselves are susceptible to such attacks and can be compromised. Hence, the robustness of these detectors is critical in maintaining the security of embedded systems. The focus of this study is to evaluate the robustness of digital circuits and delay-based digital detectors against a new type of FIA called Power-Off Attack (POA). POA occurs when the power to the chip is turned off, and the detectors are not active. Following a POA attack, the circuit or its detectors may not function properly when the power is turned back on, which can allow other attacks to be applied without being detected if the detectors are less sensitive. This study implements two detectors on Xilinx Artix-7 FPGAs and examines the impact of heating cycles on detector characteristics when the FPGA is in various states, including power-off, power-on, and inactive states (such as clock-freezing mode). Our experiments reveal that heating cycles in power-off mode can alter the FPGA component delays and the accuracy of its detectors, which highlights the vulnerability of these systems to POA and potential issues for embedded system security. © 2023 IEEE.
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| 7. |
- Estiri, Seyedeh Newsha, et al.
(författare)
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A Low-Cost Stochastic Computing-based Fuzzy Filtering for Image Noise Reduction
- 2022
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Ingår i: 2022 Ieee 13th International Green And Sustainable Computing Conference (Igsc). - New York : IEEE. - 9781665465502 ; , s. 157-162
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Konferensbidrag (refereegranskat)abstract
- Images are often corrupted with noise. As a result, noise reduction is an important task in image processing. Common noise reduction techniques, such as mean or median filtering, lead to blurring of the edges in the image, while fuzzy filters are able to preserve the edge information. In this work, we implement an efficient hardware design for a well-known fuzzy noise reduction filter based on stochastic computing. The filter consists of two main stages: edge detection and fuzzy smoothing. The fuzzy difference, which is encoded as bit-streams, is used to detect edges. Then, fuzzy smoothing is done to average the pixel value based on eight directions. Our experimental results show a significant reduction in the hardware area and power consumption compared to the conventional binary implementation while preserving the quality of the results. ©IEEE
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| 8. |
- Jamshidi, Vahid, et al.
(författare)
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MagCiM : A Flexible and Non-Volatile Computing-in-Memory Processor for Energy-Efficient Logic Computation
- 2022
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Ingår i: IEEE Access. - Piscataway, NJ : IEEE. - 2169-3536. ; 10, s. 35445-35459
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a high-performance and energy efficient processor exploiting a Magnetoresistive-based Computing-in-Memory array architecture (so-called MagCiM processor), to perform Boolean logic functions on operands stored in a memory array. The proposed processor efficiently addresses the memory wall and the leakage power consumption problems in conventional processors. The MagCiM processor utilizes mCell memory, a class of Magnetoresistive memory employing only Magnetic Tunnel Junction (MTJ) devices, to realize both computation-in-memory and on-chip instruction and data memories. The mCell memory is characterized by almost zero leakage power, high integration density, high level of reliability, and compatibility with the CMOS VLSI fabrication process. The circuit-level simulation results through comparisons with the previous work reveal that the MagCiM processor provides low occupation area, low power, and energy consumption and offers Normally-off instant-on computing capability, which makes it very suitable for embedded system applications. Based on our evaluations, a conventional processor based on the well-known MIPS architecture consumes about 13 times more energy while having 1.5 times more delay than the MagCiM processor. © 2013 IEEE.
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| 9. |
- Kazemi, Zahra, et al.
(författare)
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An Offline Hardware Security Assessment Approach using Symbol Assertion and Code Shredding
- 2022
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Ingår i: Proceedings of the Twenty Third International Symposium on Quality Electronic Design. - : IEEE. - 9781665494663 - 9781665494656 - 9781665494670
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Konferensbidrag (refereegranskat)abstract
- This paper presents an evaluation approach to analyze and prioritize the embedded software vulnerabilities against FIAs by using symbolic execution. The proposed approach is based on the code review analysis and highlights the potential software weakness points. It uses LLVM and its add-on named KLEE tool, which applies the symbolic assertion into the code under review. These tools are employed to obtain a vulnerability factor that is used to spot the corner cases in the execution paths of the code blocks. A case study has shown the effectiveness of the generated assertions in pinpointing the actual vulnerabilities. © 2022 IEEE.
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| 10. |
- Mansoor, Ali, et al.
(författare)
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Optimized reverse converters with multibit soft error correction support at 7nm technology
- 2023
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Ingår i: Computers & electrical engineering. - Oxford : Elsevier. - 0045-7906 .- 1879-0755. ; 107
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Tidskriftsartikel (refereegranskat)abstract
- Residue number system (RNS) speeds up digital signal processing systems involving dominant addition and multiplication. Addition and multiplication are accelerated further and performed with a balanced performance on one-hot coded (OHC) residue digits. However, the high complexity of the RNS reverse converter (RC) may kill the performance gain. This paper proposes a high-speed and scalable RNS-RC for both regular and one-hot RNS. For redundant RNS (RRNS), an RRNS-RC is proposed, which based on majority-voting between OHC residue digits, corrects multibit soft errors occurring in a single residue channel. With pass-transistor logic and low-power FinFETs, the proposed RCs are optimized. The simulated RRNS-RC corrected 98.5% of soft errors, while consuming 7, 6.2 and 0.4% of the system's area, leakage power and dynamic power, respectively. As compared to the leading lookup table RC in the literature, RNS-RC exhibited 10.3X, 4.4X and 1.8X savings in area, average power, and delay, respectively. © 2023 The Author(s)
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