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| 2. |
- Azam, Sher, 1971-, et al.
(författare)
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High Power, Single Stage SiGaN HEMT Class EPower Amplifier at GHz Frequencies
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Annan publikation (övrigt vetenskapligt/konstnärligt)abstract
- A high power single stage class E power amplifier is implemented with lumped elements at 0.89-1.02GHz using Silicon GaN High Electron Mobility Transistor as an active device. The maximum drain efficiency (DE) and power added efficiency (PAE) of 67 and 65 % respectively is obtained with a maximum output power of 42.2 dBm (~ 17 W) and amaximum power gain of 15 dB. We obtained good results at all measured frequencies.
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| 3. |
- Fritzin, Jonas, et al.
(författare)
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A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS
- 2010
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Ingår i: Analog Integrated Circuits and Signal Processing. - : Springer Science Business Media. - 0925-1030 .- 1573-1979. ; 64:3, s. 241-247
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Tidskriftsartikel (refereegranskat)abstract
- This paper describes the design of a power amplifier (PA) for 802.11n WLAN fabricated in 65 nm CMOS technology. The PA utilizes 3.3 V thick gate oxide (5.2 nm) transistors and a two-stage differential configuration with integrated transformers for input and interstage matching. A methodology used to extract the layout parasitics from electromagnetic (EM) simulations is described. For a 72.2 Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6 and 19.6 dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17 dBm.
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| 4. |
- Fritzin, Jonas, et al.
(författare)
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A +32dBm 1.85GHz Class-D Outphasing RF PA in 130nm CMOS for WCDMA/LTE
- 2011
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Ingår i: Proceedings of the IEEE European Solid-State Circuits Conference (ESSCIRC). - : IEEE. - 9781457707025 - 9781457707032 ; , s. 127-130
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Konferensbidrag (refereegranskat)abstract
- This paper presents a Class-D outphasing RF Power Amplifier (PA) which can operate at a 5.5V supply and deliver +32dBm at 1.85 GHz in a standard 130nm CMOS technology. The PA utilizes four on-chip transformers to combine the outputs of eight Class-D stages. The Class-D stages utilize a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5 V supply in the 1.2/2.5 V 130nm process without excessive device voltage stress. Spectral and modulation requirements were met when a WCDMA and an LTE signal (20 MHz, 16-QAM) were applied to the outphasing PA. At +28.0 dBm channel power for the WCDMA signal, the measured ACLR at 5 MHz and 10 MHz offset were −38.7 dBc and −47.0 dBc, respectively. At +24.9 dBm channel power for the LTE signal, the measured ACLR at 20MHz offset was −34.9 dBc. To the authors' best knowledge, the PA presented in this work has a 3.9 dB higher output power compared to published CMOS Class-D RF PAs.
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| 5. |
- Fritzin, Jonas, 1980-, et al.
(författare)
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A 72.2Mbit/s LC-Based Power Amplifier in 65nm CMOS for 2.4GHz 802.11n WLAN
- 2008
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Ingår i: Proceedings of the 15th Mixed Design of Integrated Circuits and Systems (MIXDES) Conference. - : IEEE. - 9788392263272 ; , s. 155-158
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Konferensbidrag (refereegranskat)abstract
- This paper describes the design and evaluation of a power amplifier (PA) for WLAN 802.11n in 65nm CMOS technology. The PA utilizes 3.3V thick-gate oxide (5.2nm) transistors and a two-stage differential configuration with two integrated inductors for input and interstage matching. For a 72.2Mbit/s, 64-QAM 802.11n OFDM signal at an average and peak output power of 9.4dBm and 17.4dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 14dBm.
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| 6. |
- Fritzin, Jonas, 1980-, et al.
(författare)
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A 72.2Mbit/s Transformer-Based Power Amplifier in 65nm CMOS for 2.4GHz 802.11n WLAN
- 2008
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Ingår i: Proceedings of 26th IEEE NORCHIP Conference. - : IEEE. - 9781424424924 ; , s. 54-56
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Konferensbidrag (refereegranskat)abstract
- This paper describes the design of a power amplifier (PA) for WLAN 802.11n fabricated in 65 nm CMOS technology. The PA utilizes 3.3 V thick-gate oxide (5.2 nm) transistors and a two-stage differential configuration with two integrated transformers for input and interstage matching. For a 72.2 Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6 dBm and 19.6 dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17 dBm.
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| 7. |
- Fritzin, Jonas, et al.
(författare)
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A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS
- 2010
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Ingår i: Proceedings of the ESSCIRC, 2010. - Seville : IEEE. - 9781424466627 ; , s. 310-313
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Konferensbidrag (refereegranskat)abstract
- This paper presents a low-power Class-D stage featuring a new harmonic reduction technique, which cancels the 3rd harmonic and reduces the 5th harmonic. The technique creates a voltage level of VDD/2 from a single supply voltage to shape the drain voltage, uses only digital circuits and eliminates the short-circuit current present in inverter-based Class-D stages. From a single Class-D stage operating at 900MHz, the measured output power is +5.1dBm with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 73% and 59% for a 1.2V supply, while 2nd to 4th harmonics are measured to be -37dBc without any filtering. Connecting two Class-D stages to a PCB-mounted transformer in an outphasing configuration, the overall amplifier is linear enough to amplify EDGE 8-PSK and WCDMA modulated signals at 900MHz without pre-distortion of the input signals or any other linearization technique.
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| 8. |
- Fritzin, Jonas, et al.
(författare)
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A Class-D Stage with Harmonic Suppression and DLL-Based Phase Generation
- 2012
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Ingår i: 2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS). - : Lida Ray Technologies Inc.. - 9781467325257 - 9781467325264 ; , s. 45-48
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Konferensbidrag (refereegranskat)abstract
- This paper presents a Class-D stage with 3rd harmonic suppression operating at 2V(DD) (i.e., twice the nominal supply voltage). A DLL-based phase generator is used to generate the phases of the driving signals and by modifying the driver stage 5th harmonic suppression is also possible. The output stage and drivers are based on inverters only, where the short-circuit current is eliminated in the output stage. Operating at 1 GHz, the simulated output power is +19.4 dBm utilizing a 1-V supply and a 5-Omega load, with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 72% and 52%, respectively, including power dissipation in the DLL-based phase generator and drivers. The 3rd harmonic is suppressed 23 dB (-33 dBc) compared to a conventional Class-D stage.
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