| 1. |
- Eriksson, Therese, 1992-, et al.
(författare)
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Polyketones as Host Materials for Solid Polymer Electrolytes
- 2020
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Ingår i: Journal of the Electrochemical Society. - : ELECTROCHEMICAL SOC INC. - 0013-4651 .- 1945-7111. ; 167:7
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Tidskriftsartikel (refereegranskat)abstract
- While solid polymer electrolytes (SPEs) have great potential for use in future lithium-based batteries, they do, however, not display conductivity at a sufficient level as compared to liquid electrolytes. To reach the needed requirements of lithium batteries it is therefore necessary to explore new materials classes to serve as novel polymer hosts. In this work, SPEs based on the polyketone poly(3,3-dimethylpentane-2,4-dione) were investigated. Polyketones are structurally similar to several polycarbonate and polyester SPE hosts investigated before but have, due to the lack of additional oxygen atoms in the coordinating motif, even more electronwithdrawing carbonyl groups and could therefore display better properties for coordination to the salt cation. In electrolyte compositions comprising 25-40 wt% LiTFSI salt, it was observed that this polyketone indeed conducts lithium ions with a high cation transference number, but that the ionic conductivity is limited by the semi-crystallinity of the polymer matrix. The crystallinity decreases with increasing salt content, and a fully amorphous SPE can be produced at 40 wt% salt, accompanied by an ionic conductivity of 3 x 10(-7) S cm(-1) at 32 degrees C. This opens up for further exploration of polyketone systems for SPE-based batteries.
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| 2. |
- Izosimov, Viacheslav, et al.
(författare)
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Optimization of Assertion Placement in Time-Constrained Embedded Systems
- 2011
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Ingår i: European Test Symposium (ETS2011), Trondheim, Norway, May 23-27, 2011.. - : IEEE. - 9781457704833 - 9780769544335
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Konferensbidrag (refereegranskat)abstract
- We present an approach for optimization of assertion placement in time-constrained HW/SW modules for detection of errors due to transient and intermittent faults. During the design phases, these assertions have to be inserted into the executable code and, hence, will always be executed with the corresponding code branches. As the result, they can significantly increase execution time of a module, in particular, contributing to a much longer execution of the worst case, and cause deadline misses. Assertions have different characteristics such as tightness (or "local error coverage") and execution latency. Taking into account these properties can increase efficiency of assertion checks in time-constrained embedded HW/SW modules. We have developed a design optimization framework, which (1) identifies candidate locations for assertions, (2) associates a candidate assertion to each location, and (3) selects a set of assertions in terms of performance degradation and assertion tightness. Experimental results have shown the efficiency of the proposed techniques.
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| 3. |
- Izosimov, Viacheslav, et al.
(författare)
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Time-Constraint-Aware Optimization of Assertions in Embedded Software
- 2012
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Ingår i: Journal of electronic testing. - : Springer Verlag (Germany). - 0923-8174 .- 1573-0727. ; 28:4, s. 469-486
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Tidskriftsartikel (refereegranskat)abstract
- Technology shrinking and sensitization have led to more and more transient faults in embedded systems. Transient faults are intermittent and non-predictable faults caused by external events, such as energetic particles striking the circuits. These faults do not cause permanent damages, but may affect the running applications. One way to ensure the correct execution of these embedded applications is to keep debugging and testing even after shipping of the systems, complemented with recovery/restart options. In this context, the executable assertions that have been widely used in the development process for design validation can be deployed again in the final product. In this way, the application will use the assertion to monitor itself under the actual execution and will not allow erroneous out-of-the-specification behavior to manifest themselves. This kind of software-level fault tolerance may represent a viable solution to the problem of developing commercial off-the-shelf embedded systems with dependability requirements. But software-level fault tolerance comes at a computational cost, which may affect time-constrained applications. Thus, the executable assertions shall be introduced at the best possible points in the application code, in order to satisfy timing constraints, and to maximize the error detection efficiency. We present an approach for optimization of executable assertion placement in time-constrained embedded applications for the detection of transient faults. In this work, assertions have different characteristics such as tightness, i.e., error coverage, and performance degradation. Taking into account these properties, we have developed an optimization methodology, which identifies candidate locations for assertions and selects a set of optimal assertions with the highest tightness at the lowest performance degradation. The set of selected assertions is guaranteed to respect the real-time deadlines of the embedded application. Experimental results have shown the effectiveness of the proposed approach, which provides the designer with a flexible infrastructure for the analysis of time-constrained embedded applications and transient-fault-oriented executable assertions.
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| 4. |
- Johansson, Isabell, et al.
(författare)
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Improving the Electrochemical Stability of a Polyester-Polycarbonate Solid Polymer Electrolyte by Zwitterionic Additives
- 2022
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Ingår i: ACS Applied Energy Materials. - : American Chemical Society (ACS). - 2574-0962. ; 5:8, s. 10002-10012
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Tidskriftsartikel (refereegranskat)abstract
- Rechargeable batteries with solid polymer electrolytes (SPEs), Li-metal anodes, and high-voltage cathodes like LiNixMnyCozO2 (NMC) are promising next-generation high-energy-density storage solutions. However, these types of cells typically experience rapid failure during galvanostatic cycling, visible as an incoherent voltage noise during charging. Herein, two imidazolium-based zwitterions, with varied sulfonate-bearing chain length, are added to a poly(epsilon-caprolactone-co-trimethylene carbonate):LiTFSI electrolyte as cycling-enhancing additives to study their effect on the electrochemical stability of the electrolyte and the cycling performance of half-cells with NMC cathodes. The oxidative stability is studied with two different voltammetric methods using cells with inert working electrodes: the commonly used cyclic voltammetry and staircase voltammetry. The specific effects of the NMC cathode on the electrolyte stability is moreover investigated with cutoff increase cell cycling (CICC) to study the chemical and electrochemical compatibility between the active material and the SPE. Zwitterionic additives proved to enhance the electrochemical stability of the SPE and to facilitate improved galvanostatic cycling stability in half-cells with NMC by preventing the decomposition of LiTFSI at the polymer-cathode interface, as indicated by X-ray photoelectron spectroscopy (XPS).
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| 5. |
- Leung, Edison, et al.
(författare)
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Alterations in brain synaptic proteins and mRNAs in mood disorders : a systematic review and meta-analysis of postmortem brain studies
- 2022
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Ingår i: Molecular Psychiatry. - : Springer Nature. - 1359-4184 .- 1476-5578. ; 27:3, s. 1362-1372
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Forskningsöversikt (refereegranskat)abstract
- The pathophysiological mechanisms underlying bipolar (BD) and major depressive disorders (MDD) are multifactorial but likely involve synaptic dysfunction and dysregulation. There are multiple synaptic proteins but three synaptic proteins, namely SNAP-25, PSD-95, and synaptophysin, have been widely studied for their role in synaptic function in human brain postmortem studies in BD and MDD. These studies have yielded contradictory results, possibly due to the small sample size and sourcing material from different cortical regions of the brain. We performed a systematic review and meta-analysis to understand the role of these three synaptic proteins and other synaptic proteins, messenger RNA (mRNA) and their regional localizations in BD and MDD. A systematic literature search was conducted and the review is reported in accordance with the MOOSE Guidelines. Meta-analysis was performed to compare synaptic marker levels between BD/MDD groups and controls separately. 1811 papers were identified in the literature search and screened against the preset inclusion and exclusion criteria. A total of 72 studies were screened in the full text, of which 47 were identified as eligible to be included in the systematic review. 24 of these 47 papers were included in the meta-analysis. The meta-analysis indicated that SNAP-25 protein levels were significantly lower in BD. On average, PSD-95 mRNA levels were lower in BD, and protein levels of SNAP-25, PSD-95, and syntaxin were lower in MDD. Localization analysis showed decreased levels of PSD-95 protein in the frontal cortex. We found specific alterations in synaptic proteins and RNAs in both BD and MDD. The review was prospectively registered online in PROSPERO international prospective register of systematic reviews, registration no. CRD42020196932.
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| 6. |
- Sjökvist, Niclas, et al.
(författare)
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State retention flip flop architectures with different tradeoffs using crystalline indium gallium zinc oxide transistors implemented in a 32-bit normally-off microprocessor
- 2014
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Ingår i: Japanese Journal of Applied Physics. - : Japan Society of Applied Physics. - 0021-4922 .- 1347-4065. ; 53:4, s. 04EE10-
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Tidskriftsartikel (refereegranskat)abstract
- As leakage power continues to increase when transistor sizes are downscaled, it becomes increasingly hard to achieve low power consumption in modern chips. Normally-off processors use state-retention and non-volatile circuits to make power gating more efficient with less static power. In this paper, we propose two novel state-retention flip-flop designs based on a parallel and series retention circuit architectures utilizing crystalline indium gallium zinc oxide transistors, which can achieve state retention with zero static power. To demonstrate the application of these different designs, they are implemented in a 32-bit normally-off microprocessor with an energy break-even time of 1.47 mu s for the parallel type design and 0.93 mu s for the series type design, at a clock frequency of 15 MHz. We show that decreasing the power supply duty cycle to 0.9%, the average current of the processor core can be decreased by over 99% using either type of flip-flop.
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| 7. |
- Wang, Zheng, et al.
(författare)
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Axial Spondylometaphyseal Dysplasia Is Caused by C21orf2 Mutations.
- 2016
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Ingår i: PLOS ONE. - : Public Library of Science (PLoS). - 1932-6203. ; 11:3
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Tidskriftsartikel (refereegranskat)abstract
- Axial spondylometaphyseal dysplasia (axial SMD) is an autosomal recessive disease characterized by dysplasia of axial skeleton and retinal dystrophy. We conducted whole exome sequencing and identified C21orf2 (chromosome 21 open reading frame 2) as a disease gene for axial SMD. C21orf2 mutations have been recently found to cause isolated retinal degeneration and Jeune syndrome. We found a total of five biallelic C21orf2 mutations in six families out of nine: three missense and two splicing mutations in patients with various ethnic backgrounds. The pathogenic effects of the splicing (splice-site and branch-point) mutations were confirmed on RNA level, which showed complex patterns of abnormal splicing. C21orf2 mutations presented with a wide range of skeletal phenotypes, including cupped and flared anterior ends of ribs, lacy ilia and metaphyseal dysplasia of proximal femora. Analysis of patients without C21orf2 mutation indicated genetic heterogeneity of axial SMD. Functional data in chondrocyte suggest C21orf2 is implicated in cartilage differentiation. C21orf2 protein was localized to the connecting cilium of the cone and rod photoreceptors, confirming its significance in retinal function. Our study indicates that axial SMD is a member of a unique group of ciliopathy affecting skeleton and retina.
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| 8. |
- Zhang, Ying, et al.
(författare)
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BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature
- 2022
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1063-8210 .- 1557-9999. ; 30:11, s. 1677-1690
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Tidskriftsartikel (refereegranskat)abstract
- This article presents a bounded model checking (BMC)-based temperature-aware software-based self-testing (SBST) technique to test worst case delay faults within the highest temperature range. The BMC-based SBST method first defines the sequential constraint. It develops a sequentially constrained automatic test pattern generation (ATPG) to ensure that the generated delay test patterns can emerge in functional mode. It then uses the processors multiple-level information to reduce the model complexity, avoid aborts due to time-outs during the BMC process, and generate test programs automatically. A temperature-aware SBST method has then been developed to ensure that the test temperature is within the specified range and test the worst case delays under high temperature. Experimental results demonstrate that the proposed technique achieves an extremely high coverage for delay faults and effectively avoids yield loss caused by the overtesting problem. Its test quality also outperforms that of the existing methods. The generated SBST programs are successful and efficient in testing worst case delay faults under high temperature.
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| 9. |
- Zhang, Ying, et al.
(författare)
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Temperature-Aware Software-Based Self-Testing for Delay Faults
- 2015
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Ingår i: <em>Proc. Design, Automation and Test in Europe Conference (DATE’15), Grenoble, France, Mar. 9-13, 2015.</em>. - 9783981537048
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Konferensbidrag (refereegranskat)abstract
- Delay defects under high temperature have been one of the most critical factors to affect the reliability of computer systems, and the current test methods don’t address this problem properly. In this paper, a temperature-aware software-based selftesting (SBST) technique is proposed to self-heat the processors within a high temperature range and effectively test delay faults under high temperature. First, it automatically generates highquality test programs through automatic test instruction generation (ATIG), and avoids over-testing caused by nonfunctional patterns. Second, it exploits two effective powerintensive program transformations to self-heat up the processors internally. Third, it applies a greedy algorithm to search the optimized schedule of the test templates in order to generate the test program while making sure that the temperature of the processor under test is within the specified range. Experimental results show that the generated program is successful to guarantee delay test within the given temperature range, and achieves high test performance with functional patterns.
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