1. |
|
|
2. |
|
|
3. |
- Cozen, W., et al.
(författare)
-
A meta-analysis of Hodgkin lymphoma reveals 19p13.3 TCF3 as a novel susceptibility locus
- 2014
-
Ingår i: Nature Communications. - : Springer Science and Business Media LLC. - 2041-1723. ; 5, s. 3856-
-
Tidskriftsartikel (refereegranskat)abstract
- Recent genome-wide association studies (GWAS) of Hodgkin lymphoma (HL) have identified associations with genetic variation at both HLA and non-HLA loci; however, much of heritable HL susceptibility remains unexplained. Here we perform a meta-analysis of three HL GWAS totaling 1,816 cases and 7,877 controls followed by replication in an independent set of 1,281 cases and 3,218 controls to find novel risk loci. We identify a novel variant at 19p13.3 associated with HL (rs1860661; odds ratio (OR) = 0.81, 95% confidence interval (95% CI) = 0.76-0.86, P-combined 3.5 x 10(-10)), located in intron 2 of TCF3 (also known as E2A), a regulator of B-and T-cell lineage commitment known to be involved in HL pathogenesis. This meta-analysis also notes associations between previously published loci at 2p16, 5q31, 6p31, 8q24 and 10p14 and HL subtypes. We conclude that our data suggest a link between the 19p13.3 locus, including TCF3, and HL risk.
|
|
4. |
|
|
5. |
|
|
6. |
|
|
7. |
|
|
8. |
|
|
9. |
|
|
10. |
- Le Guillou, Y, et al.
(författare)
-
Highly integrated direct conversion receiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic range continuous-time ΣΔ ADC
- 2005
-
Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200. ; 40:2, s. 403-411
-
Tidskriftsartikel (refereegranskat)abstract
- This paper describes a highly digitized direct conversion receiver of a single-chip quadruple-band RF transceiver that meets GSM/GPRS and EDGE requirements. The chip uses an advanced 0.25-mum BiCMOS technology. The I and Q on-chip fifth-order single-bit continuous-time sigma-delta (SigmaDelta) ADC has 84-dB dynamic range over a total bandwidth of +/-135 kHz for an active area of 0.4 mm(2). Hence, most of the channel filtering is realized in a CMOS IC where digital processing-is achieved at a lower cost. The systematic analysis of dc offset at each stage of the design enables to perform the dc offset cancellation loop in the digital domain as well. The receiver operates at 2.7 V with a current consumption of 75 mA. A first-order substrate coupling analysis enables to optimize the floor plan strategy. As a result, the receiver has an area of 1.8 mm(2).
|
|