| 1. |
- Bae, Cheolyong, et al.
(författare)
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Improved Implementation Approaches for 512-tap 60 GSa/s Chromatic Dispersion FIR Filters
- 2018
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Ingår i: 2018 CONFERENCE RECORD OF 52ND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS, AND COMPUTERS. - : IEEE. - 9781538692189 ; , s. 213-217
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Konferensbidrag (refereegranskat)abstract
- In optical communication the non-ideal properties of the fibers lead to pulse widening from chromatic dispersion. One way to compensate for this is through digital signal processing. In this work, two architectures for compensation are compared. Both are designed for 60 GSa/s and 512 filter taps and implemented in the frequency domain using FFTs. It is shown that the high-speed requirements introduce constraints on possible architectural choices. In this work, it is shown that it is not required to use two overlapping FFTs to obtain continuous filtering. In addition, efficient highly parallel implementation of FFTs is discussed and an unproved FFT compared to our earlier work is proposed. The results are compared to using an approach with a shorter FFT and FIR filters.
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| 2. |
- Boopal, Padma Prasad, et al.
(författare)
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A Reconfigurable FFT Architecture for Variable-Length and Multi-Streaming OFDM Standards
- 2013
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Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS), 2013. - : IEEE. - 9781467357609 ; , s. 2066-2070
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Konferensbidrag (refereegranskat)abstract
- This paper presents a reconfigurable FFT architecture for variable-length and multi-streaming WiMax wireless standard. The architecture processes 1 stream of 2048-point FFT, up to 2 streams of 1024-point FFT or up to 4 streams of 512-point FFT. The architecture consists of a modified radix-2 single delay feedback (SDF) FFT. The sampling frequency of the system is varied in accordance with the FFT length. The latch-free clock gating technique is used to reduce power consumption. The proposed architecture has been synthesized for the Virtex-6 XCVLX760 FPGA. Experimental results show that the architecture achieves the throughput that is required by the WiMax standard and the design has additional features compared to the previous approaches. The design uses 1% of the total available FPGA resources and maximum clock frequency of 313.67 MHz is achieved. Furthermore, this architecture can be expanded to suit other wireless standards.
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| 3. |
- Chen, Sau-Gee, et al.
(författare)
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Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures
- 2014
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 61:10, s. 2869-2877
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.
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| 4. |
- Garrido Gálvez, Mario, et al.
(författare)
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A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
- 2017
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1063-8210 .- 1557-9999. ; 25:1, s. 375-379
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents a novel 4096-point radix-4 memory-based fast Fourier transform (FFT). The proposed architecture follows a conflict-free strategy that only requires a total memory of size N and a few additional multiplexers. The control is also simple, as it is generated directly from the bits of a counter. Apart from the low complexity, the FFT has been implemented on a Virtex-5 field programmable gate array (FPGA) using DSP slices. The goal has been to reduce the use of distributed logic, which is scarce in the target FPGA. With this purpose, most of the hardware has been implemented in DSP48E. As a result, the proposed FPGA is efficient in terms of hardware resources, as is shown by the experimental results.
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| 5. |
- Garrido Gálvez, Mario
(författare)
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A New Representation of FFT Algorithms Using Triangular Matrices
- 2016
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 63:10, s. 1737-1745
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Tidskriftsartikel (refereegranskat)abstract
- In this paper we propose a new representation for FFT algorithms called the triangular matrix representation. This representation is more general than the binary tree representation and, therefore, it introduces new FFT algorithms that were not discovered before. Furthermore, the new representation has the advantage that it is simple and easy to understand, as each FFT algorithm only consists of a triangular matrix. Besides, the new representation allows for obtaining the exact twiddle factor values in the FFT flow graph easily. This facilitates the design of FFT hardware architectures. As a result, the triangular matrix representation is an excellent alternative to represent FFT algorithms and it opens new possibilities in the exploration and understanding of the FFT.
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| 6. |
- Garrido Gálvez, Mario, et al.
(författare)
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A Serial Commutator Fast Fourier Transform Architecture for Real-Valued Signals
- 2018
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 65:11, s. 1693-1697
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents a novel pipelined architecture to compute the fast Fourier transform of real input signals in a serial manner, i.e., one sample is processed per cycle. The proposed architecture, referred to as real-valued serial commutator, achieves full hardware utilization by mapping each stage of the fast Fourier transform (FFT) to a half-butterfly operation that operates on real input signals. Prior serial architectures to compute FFT of real signals only achieved 50% hardware utilization. Novel data-exchange and data-reordering circuits are also presented. The complete serial commutator architecture requires 2 log(2) N - 2 real adders, log(2) N - 2 real multipliers, and N + 9 log(2) N - 19 real delay elements, where N represents the size of the FFT.
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| 7. |
- Garrido Gálvez, Mario, et al.
(författare)
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Accurate Rotations Based on Coefficient Scaling
- 2011
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 58:10, s. 662-666
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents a novel approach for improving the accuracy of rotations implemented by complex multipliers, based on scaling the complex coefficients that define these rotations. A method for obtaining the optimum coefficients that lead to the lowest error is proposed. This approach can be used to get more accurate rotations without increasing the coefficient word length and to reduce the word length without increasing the rotation error. This brief analyzes two different situations where the optimization method can be applied: rotations that can be optimized independently and sets of rotations that require the same scaling. These cases appear in important signal processing algorithms such as the discrete cosine transform and the fast Fourier transform (FFT). Experimental results show that the use of scaling for the coefficients clearly improves the accuracy of the algorithms. For instance, improvements of about 8 dB in the Frobenius norm of the FFT are achieved with respect to using non-scaled coefficients.
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| 8. |
- Garrido Gálvez, Mario, et al.
(författare)
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Continuous-flow variable-length memoryless linear regression architecture
- 2013
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Ingår i: Electronics Letters. - : Institution of Engineering and Technology (IET). - 0013-5194 .- 1350-911X. ; 49:24, s. 1567-1568
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Tidskriftsartikel (refereegranskat)abstract
- A pipelined circuit to calculate linear regression is presented. The proposed circuit has the advantages that it can process a continuous flow of data, it does not need memory to store the input samples and supports variable length that can be reconfigured in run time. The circuit is efficient in area, as it consists of a small number of adders, multipliers and dividers. These features make it very suitable for real-time applications, as well as for calculating the linear regression of a large number of samples.
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| 9. |
- Garrido Gálvez, Mario, et al.
(författare)
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CORDIC II: A New Improved CORDIC Algorithm
- 2016
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 63:2, s. 186-190
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Tidskriftsartikel (refereegranskat)abstract
- In this brief, we present the CORDIC II algorithm. Like previous CORDIC algorithms, the CORDIC II calculates rotations by breaking down the rotation angle into a series of microrotations. However, the CORDIC II algorithm uses a novel angle set, different from the angles used in previous CORDIC algorithms. The new angle set provides a faster convergence that reduces the number of adders with respect to previous approaches.
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| 10. |
- Garrido Gálvez, Mario, et al.
(författare)
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Feedforward FFT Hardware Architectures Based on Rotator Allocation
- 2018
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 65:2, s. 581-592
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we present new feedforward FFT hardware architectures based on rotator allocation. The rotator allocation approach consists in distributing the rotations of the FFT in such a way that the number of edges in the FFT that need rotators and the complexity of the rotators are reduced. Radix-2 and radix-2(k) feedforward architectures based on rotator allocation are presented in this paper. Experimental results show that the proposed architectures reduce the hardware cost significantly with respect to previous FFT architectures.
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