| 1. |
- Beal, Jacob, et al.
(författare)
-
Robust estimation of bacterial cell count from optical density
- 2020
-
Ingår i: Communications Biology. - : Springer Science and Business Media LLC. - 2399-3642. ; 3:1
-
Tidskriftsartikel (refereegranskat)abstract
- Optical density (OD) is widely used to estimate the density of cells in liquid culture, but cannot be compared between instruments without a standardized calibration protocol and is challenging to relate to actual cell count. We address this with an interlaboratory study comparing three simple, low-cost, and highly accessible OD calibration protocols across 244 laboratories, applied to eight strains of constitutive GFP-expressing E. coli. Based on our results, we recommend calibrating OD to estimated cell count using serial dilution of silica microspheres, which produces highly precise calibration (95.5% of residuals <1.2-fold), is easily assessed for quality control, also assesses instrument effective linear range, and can be combined with fluorescence calibration to obtain units of Molecules of Equivalent Fluorescein (MEFL) per cell, allowing direct comparison and data fusion with flow cytometry measurements: in our study, fluorescence per cell measurements showed only a 1.07-fold mean difference between plate reader and flow cytometry data.
|
|
| 2. |
- Klionsky, Daniel J., et al.
(författare)
-
Guidelines for the use and interpretation of assays for monitoring autophagy
- 2012
-
Ingår i: Autophagy. - : Informa UK Limited. - 1554-8635 .- 1554-8627. ; 8:4, s. 445-544
-
Forskningsöversikt (refereegranskat)abstract
- In 2008 we published the first set of guidelines for standardizing research in autophagy. Since then, research on this topic has continued to accelerate, and many new scientists have entered the field. Our knowledge base and relevant new technologies have also been expanding. Accordingly, it is important to update these guidelines for monitoring autophagy in different organisms. Various reviews have described the range of assays that have been used for this purpose. Nevertheless, there continues to be confusion regarding acceptable methods to measure autophagy, especially in multicellular eukaryotes. A key point that needs to be emphasized is that there is a difference between measurements that monitor the numbers or volume of autophagic elements (e.g., autophagosomes or autolysosomes) at any stage of the autophagic process vs. those that measure flux through the autophagy pathway (i.e., the complete process); thus, a block in macroautophagy that results in autophagosome accumulation needs to be differentiated from stimuli that result in increased autophagic activity, defined as increased autophagy induction coupled with increased delivery to, and degradation within, lysosomes (in most higher eukaryotes and some protists such as Dictyostelium) or the vacuole (in plants and fungi). In other words, it is especially important that investigators new to the field understand that the appearance of more autophagosomes does not necessarily equate with more autophagy. In fact, in many cases, autophagosomes accumulate because of a block in trafficking to lysosomes without a concomitant change in autophagosome biogenesis, whereas an increase in autolysosomes may reflect a reduction in degradative activity. Here, we present a set of guidelines for the selection and interpretation of methods for use by investigators who aim to examine macroautophagy and related processes, as well as for reviewers who need to provide realistic and reasonable critiques of papers that are focused on these processes. These guidelines are not meant to be a formulaic set of rules, because the appropriate assays depend in part on the question being asked and the system being used. In addition, we emphasize that no individual assay is guaranteed to be the most appropriate one in every situation, and we strongly recommend the use of multiple assays to monitor autophagy. In these guidelines, we consider these various methods of assessing autophagy and what information can, or cannot, be obtained from them. Finally, by discussing the merits and limits of particular autophagy assays, we hope to encourage technical innovation in the field.
|
|
| 3. |
- Ahmed, Tanvir, et al.
(författare)
-
A 512-point 8-parallel pipelined feedforward FFT for WPAN
- 2011
-
Ingår i: 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR). - : IEEE. ; , s. 981-984
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a 512-point feedforward FFT architecture for wireless personal area network (WPAN). The architecture processes a continuous flow of 8 samples in parallel, leading to a throughput of 2.64 GSamples/s. The FFT is computed in three stages that use radix-8 butterflies. This radix reduces significantly the number of rotators with respect to previous approaches based on radix-2. Besides, the proposed architecture uses the minimum memory that is required for a 512-point 8-parallel FFT. Experimental results show that besides its high throughput, the design is efficient in area and power consumption, improving the results of previous approaches. Specifically, for a wordlength of 16 bits, the proposed design consumes 61.5 mW and its area is 1.43 mm2.
|
|
| 4. |
- Ambuluri, Sreehari, et al.
(författare)
-
New Radix-2 and Radix-22 Constant Geometry Fast Fourier Transform Algorithms For GPUs
- 2013
-
Konferensbidrag (refereegranskat)abstract
- This paper presents new radix-2 and radix-22 constant geometry fast Fourier transform (FFT) algorithms for graphics processing units (GPUs). The algorithms combine the use of constant geometry with special scheduling of operations and distribution among the cores. Performance tests on current GPUs show a significant improvements compared to the most recent version of NVIDIA’s well-known CUFFT, achieving speedups of up to 5.6x.
|
|
| 5. |
- Andersson, Rikard, et al.
(författare)
-
Using Rotator Transformations to Simplify FFT Hardware Architectures
- 2020
-
Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 67:12, s. 4784-4793
-
Tidskriftsartikel (refereegranskat)abstract
- In this paper, we present a new approach to simplify fast Fourier transform (FFT) hardware architectures. The new approach is based on a group of transformations called decimation, reduction, center, move and merge. By combining them it is possible to transform the rotators at different FFT stages, move them to other stages and merge them in such a way that the resulting rotators are simpler than the original ones. The proposed approach can be combined with other existing techniques such coefficient selection and shift-and-add implementation, or rotator allocation in order to obtain low-complexity FFT hardware architectures. To show the effectiveness of the proposed approach, it has been applied to single-path delay feedback (SDF) FFT hardware architectures, where it is observed that the complexity of the rotators is reduced up to 33%.
|
|
| 6. |
- Bae, Cheolyong, et al.
(författare)
-
Improved Implementation Approaches for 512-tap 60 GSa/s Chromatic Dispersion FIR Filters
- 2018
-
Ingår i: 2018 CONFERENCE RECORD OF 52ND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS, AND COMPUTERS. - : IEEE. - 9781538692189 ; , s. 213-217
-
Konferensbidrag (refereegranskat)abstract
- In optical communication the non-ideal properties of the fibers lead to pulse widening from chromatic dispersion. One way to compensate for this is through digital signal processing. In this work, two architectures for compensation are compared. Both are designed for 60 GSa/s and 512 filter taps and implemented in the frequency domain using FFTs. It is shown that the high-speed requirements introduce constraints on possible architectural choices. In this work, it is shown that it is not required to use two overlapping FFTs to obtain continuous filtering. In addition, efficient highly parallel implementation of FFTs is discussed and an unproved FFT compared to our earlier work is proposed. The results are compared to using an approach with a shorter FFT and FIR filters.
|
|
| 7. |
- Boopal, Padma Prasad, et al.
(författare)
-
A Reconfigurable FFT Architecture for Variable-Length and Multi-Streaming OFDM Standards
- 2013
-
Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS), 2013. - : IEEE. - 9781467357609 ; , s. 2066-2070
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a reconfigurable FFT architecture for variable-length and multi-streaming WiMax wireless standard. The architecture processes 1 stream of 2048-point FFT, up to 2 streams of 1024-point FFT or up to 4 streams of 512-point FFT. The architecture consists of a modified radix-2 single delay feedback (SDF) FFT. The sampling frequency of the system is varied in accordance with the FFT length. The latch-free clock gating technique is used to reduce power consumption. The proposed architecture has been synthesized for the Virtex-6 XCVLX760 FPGA. Experimental results show that the architecture achieves the throughput that is required by the WiMax standard and the design has additional features compared to the previous approaches. The design uses 1% of the total available FPGA resources and maximum clock frequency of 313.67 MHz is achieved. Furthermore, this architecture can be expanded to suit other wireless standards.
|
|
| 8. |
- Chen, Sau-Gee, et al.
(författare)
-
Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures
- 2014
-
Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 61:10, s. 2869-2877
-
Tidskriftsartikel (refereegranskat)abstract
- This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.
|
|
| 9. |
- Garrido Gálvez, Mario, et al.
(författare)
-
A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
- 2017
-
Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1063-8210 .- 1557-9999. ; 25:1, s. 375-379
-
Tidskriftsartikel (refereegranskat)abstract
- This brief presents a novel 4096-point radix-4 memory-based fast Fourier transform (FFT). The proposed architecture follows a conflict-free strategy that only requires a total memory of size N and a few additional multiplexers. The control is also simple, as it is generated directly from the bits of a counter. Apart from the low complexity, the FFT has been implemented on a Virtex-5 field programmable gate array (FPGA) using DSP slices. The goal has been to reduce the use of distributed logic, which is scarce in the target FPGA. With this purpose, most of the hardware has been implemented in DSP48E. As a result, the proposed FPGA is efficient in terms of hardware resources, as is shown by the experimental results.
|
|
| 10. |
- Garrido Gálvez, Mario
(författare)
-
A New Representation of FFT Algorithms Using Triangular Matrices
- 2016
-
Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 63:10, s. 1737-1745
-
Tidskriftsartikel (refereegranskat)abstract
- In this paper we propose a new representation for FFT algorithms called the triangular matrix representation. This representation is more general than the binary tree representation and, therefore, it introduces new FFT algorithms that were not discovered before. Furthermore, the new representation has the advantage that it is simple and easy to understand, as each FFT algorithm only consists of a triangular matrix. Besides, the new representation allows for obtaining the exact twiddle factor values in the FFT flow graph easily. This facilitates the design of FFT hardware architectures. As a result, the triangular matrix representation is an excellent alternative to represent FFT algorithms and it opens new possibilities in the exploration and understanding of the FFT.
|
|
