| 1. |
- Chang, Z., et al.
(författare)
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On improved MANET network utilization
- 2012
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Ingår i: 2012 International Conference on Wireless Communications and Signal Processing, WCSP 2012.
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Konferensbidrag (refereegranskat)abstract
- Mobile ad hoc network (MANET) is a new opportunity for mobile networking using intelligent mobile terminals. However, the widely used shortest path first based routing algorithm leads to various network utilization problems. Mobile terminals have limited power, hence, power saving should be considered when terminals serve as intermediate nodes in MANET. Furthermore, ad hoc routing table calculation is distributed among all network terminals. Therefore, we also need to construct stable paths with longer lifetime in order to reduce the communication overhead introduced by route reconstruction. A less evenly distributed traffic exhausts power on the nodes in the center of the network and leads to shorter path lifetime. Such a network deployment is not fair for the internal nodes. The above problems exist for all routing protocols especially proactive routing protocols based on shortest path first algorithm OLSR. In this paper we study the MANET network utilization in term of load distribution and path lifetime. Our careful simulation results demonstrate that the standard shortest path first algorithm leads to worse load balancing and reduced path lifetime compared to our proposal. When the most unstable network topology is considered, our proposal achieves better network utilization by reducing the peak transmission per node by 15% and the standard deviation of transmission per node by 50%. The average lifetime for established paths is doubled under the most unstable topology. © 2012 IEEE.
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| 2. |
- Ciobanu, Catalin, 1983, et al.
(författare)
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Dataflow Computing with Polymorphic Registers
- 2013
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Ingår i: International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII), 2013. - 9781479901036 ; , s. 314 - 321
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Konferensbidrag (refereegranskat)abstract
- Heterogeneous systems are becoming increasingly popular for data processing. They improve performance of simple kernels applied to large amounts of data. However, sequential data loads may have negative impact. Data parallel solutions such as Polymorphic Register Files (PRFs) can potentially accelerate applications by facilitating high speed, parallel access to performance-critical data. Furthermore, by PRF customization, specific data path features are exposed to the programmer in a very convenient way. PRFs allow additional control over the registers dimensions, and the number of elements which can be simultaneously accessed by computational units. This paper shows how PRFs can be integrated in dataflow computational platforms. In particular, starting from an annotated source code, we present a compiler-based methodology that automatically generates the customized PRFs and the enhanced computational kernels that efficiently exploit them.
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| 3. |
- Ciobanu, Catalin, 1983, et al.
(författare)
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FASTER run-time reconfiguration management
- 2013
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Ingår i: Proceedings of the International Conference on Supercomputing. - New York, NY, USA : ACM. - 9781450321303 ; , s. 463-
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Konferensbidrag (refereegranskat)abstract
- The FASTER project Run-Time System Manager offloads programmers from low-level operations by performing task placement, scheduling, and dynamic FPGA reconfiguration. It also manages device fragmentation, configuration caching, pre-fetching and reuse, bitstream compression, and optimizes the system thermal and power footprints. We propose a micro-reconfiguration aware, configuration content agnostic ISA interface and a technology independent Task Configuration Microcode format targeting Maxeler Data Flow computers and Xilinx XUPV5 platforms. We achieve improved resource utilization with negligible performance overhead. Up to 4Gbps for DMA transfers, and up to 3Gbps for FPGA reconfiguration on Xilinx Virtex-5/6 devices is achieved.
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| 4. |
- Ciobanu, Catalin, 1983, et al.
(författare)
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On implementability of polymorphic register files
- 2012
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Ingår i: ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings. - 9781467325721
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Konferensbidrag (refereegranskat)abstract
- This paper studies the implementability of performance efficient multi-lane Polymorphic Register Files (PRFs). Our PRF implementation uses a 2D array of p x q linearly addressable memory banks, with customized addressing functions to avoid address routing circuits. We target one single-view and a set of four non redundant multi-view parallel memory schemes that cover all widely used access patterns in scientific and multimedia applications: 1) p x q rectangle, p·q row, p·q main and secondary diagonals; 2) p x q rectangle, p·q column, p·q main and secondary diagonals; 3) p·q row, p·q column, aligned pxq rectangle; 4) pxq, q xp rectangles (transposition). Reconfigurable hardware was chosen for the implementation due to its potential in enhancing the PRF runtime adaptability. For a proof of concept, we prototyped a 2 read, 1 write ports PRF on a Virtex-7 XC7VX1140T-2 FPGA. We consider four sizes for the 16 lanes PRFs - 16x16, 32x32, 64x64 and 128x128 and three multi-lane configurations, 8, 16 and 32, for the 128 x 128 PRF. Synthesis results suggest clock frequencies between 111 MHz and 326 MHz while utilizing less than 10% of the available LUTs. By using customized addressing functions, the LUT usage is reduced by up to 29% and the clock frequency is up to 77% higher compared to a straight-forward implementation.
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| 5. |
- Ciobanu, Catalin, 1983, et al.
(författare)
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Scalability study of polymorphic register files
- 2012
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Ingår i: 15th Euromicro Conference on Digital System Design, DSD 2012; Cesme, Izmir; Turkey; 5 September 2012 through 8 September 2012. - 9780769547985 ; , s. 803-808
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Konferensbidrag (refereegranskat)abstract
- We study the scalability of multi-lane 2D Polymorphic Register Files (PRFs) in terms of clock cycle time, chip area and power consumption. We assume an implementation which stores data in a 2D array of linearly addressable memory banks, and consider one single-view and four suitable multi-view parallel access schemes which cover all basic access patterns commonly used in scientific and multimedia applications. The PRF design features 2 read and 1 write ports, targeting the TSMC 90nm ASIC technology. We consider three PRF sizes - 32KB, 128KB and 512KB and four multi-lane configurations - 8 / 16 / 32 and 64 lanes. Synthesis results suggest that the clock frequency varies between 500MHz for a 512KB PRF with 64 vector lanes and 970Mhz for a 32KB / 8-lanes case. Estimated power consumption ranges from less than 300mW (dynamic) and 10mW (leakage) for our 8-lane, 32KB PRF up to 8.7W (dynamic) and 276mW (leakage) for a 512KB with 64 lanes. We also show the correlation among the storage capacity, the number of lanes, and the chip overall area. Furthermore, we also investigated customized addressing functions. Our experimental results suggest up to 21% increase of the clock frequency, and up to 39% combinational hardware area reduction (nearly 10% of the total area) compared to our straightforward implementations. Concerning power, we reduce dynamic power with up to 31% and leakage with nearly 24%.
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| 6. |
- Ciobanu, Catalin, 1983, et al.
(författare)
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Separable 2D Convolution with Polymorphic Register Files
- 2013
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Ingår i: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). - Berlin, Heidelberg : Springer Berlin Heidelberg. - 1611-3349 .- 0302-9743. - 9783642364235 ; 7767, s. 317-328
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Konferensbidrag (refereegranskat)abstract
- This paper studies the performance of separable 2D convolution on multi-lane Polymorphic Register Files (PRFs). We present a matrix transposition algorithm optimized for PRFs, and a 2D vectorized convolution algorithm which avoids strided memory accesses. We compare the throughput of our PRF to the NVIDIA Tesla C2050 GPU. The results show that even in bandwidth constrained systems, multi-lane PRFs can outperform the GPU for 9 × 9 or larger mask sizes.
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| 7. |
- Cristal, Adrian, et al.
(författare)
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LEGaTO: First Steps Towards Energy-Efficient Toolset for Heterogeneous Computing
- 2018
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Ingår i: ACM International Conference Proceeding Series. - New York, NY, USA : ACM. ; , s. 210-217
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Konferensbidrag (refereegranskat)abstract
- LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of magnitude energy savings from the edge to the converged cloud/HPC.
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| 8. |
- Cristal, Adrian, et al.
(författare)
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LEGaTO: Towards Energy-Efficient, Secure, Fault-tolerant Toolset for Heterogeneous Computing
- 2018
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Ingår i: Proceedings of the 15th ACM International Conference on Computing Frontiers. - New York, NY, USA : ACM. - 9781450357616 ; , s. 276-278
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Konferensbidrag (refereegranskat)abstract
- LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of magnitude energy savings from the edge to the converged cloud/HPC.
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| 9. |
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| 10. |
- Durand, Y., et al.
(författare)
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EUROSERVER: Energy efficient node for European micro-servers
- 2014
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Ingår i: 17th Euromicro Conference on Digital System Design, DSD 2014; Verona; Italy; 27 August 2014 through 29 August 2014. ; , s. 206-213
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Konferensbidrag (refereegranskat)abstract
- EUROSERVER is a collaborative project that aims to dramatically improve data centre energy-efficiency, cost, and software efficiency. It is addressing these important challenges through the coordinated application of several key recent innovations: 64-bit ARM cores, 3D heterogeneous silicon-on-silicon integration, and fully-depleted silicon-on-insulator (FD SOI) process technology, together with new software techniques for efficient resource management, including resource sharing and workload isolation. We are pioneering a system architecture approach that allows specialized silicon devices to be built even for low-volume markets where NRE costs are currently prohibitive. The EUROSERVER device will embed multiple silicon 'chiplets' on an active silicon interposer. Its system architecture is being driven by requirements from three use cases: data centres and cloud computing, telecom infrastructures, and high-end embedded systems. We will build two fully integrated full-system prototypes, based on a common micro-server board, and targeting embedded servers and enterprise servers.
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