| 1. |
- Czernohorsky, M., et al.
(författare)
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Stability of crystalline Gd(2)O(3) thin films on silicon during rapid thermal annealing
- 2008
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Ingår i: Semiconductor Science and Technology. - : IOP Publishing. - 0268-1242 .- 1361-6641. ; 23:3, s. 035010-
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Tidskriftsartikel (refereegranskat)abstract
- We investigate the impact of rapid thermal anneals on structural and electrical properties of crystalline Gd(2)O(3) layers grown on Si with different orientations. Due to additional oxygen from the annealing ambient, a structureless two-layer stack ( silicon-oxide-like and silicate-like) between the silicon and the crystalline oxide will be formed. The degradation of layers can be significantly reduced by sealing the layer with a-Si prior to annealing. For the capped layers, the effective capacitance equivalent thickness increases only slightly even after a 1000 degrees C anneal.
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| 2. |
- Lemme, Max C., 1970-, et al.
(författare)
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Complementary metal oxide semiconductor integration of epitaxial Gd(2)O(3)
- 2009
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Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 27:1, s. 258-261
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, epitaxial gadolinium oxide (Gd(2)O(3)) is reviewed as a potential high-K gate dielectric, both "as deposited" by molecular beam epitaxy as well as after integration into complementary metal oxide semiconductor (CMOS) processes. The material shows promising intrinsic properties, meeting critical ITRS targets for leakage current densities even at subnanometer equivalent oxide thicknesses. These epitaxial oxides can be integrated into a CMOS platform by a "gentle" replacement gate process. While high temperature processing potentially degrades the material, a route toward thermally stable epitaxial Gd(2)O(3) gate dielectrics is explored by carefully controlling the annealing conditions.
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| 3. |
- Efavi, J K, et al.
(författare)
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Investigation of NiAlN as gate-material for submicron CMOS technology
- 2004
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 76:1-4, s. 354-359
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Tidskriftsartikel (refereegranskat)abstract
- Nickel-Aluminium-Nitride (NiAlN) is investigated as gate material for submicron CMOS technology for the first time. The MAIN films have been reactively sputtered from a Ni0.5Al0.5 target in a mixture of argon and nitrogen gas. The influence of the reactive gas content and process temperatures on the work function is presented. Electrical properties are extracted from high and low frequency capacitance-voltage measurements (QSCV, HFCV). Resistivity measurements are shown for various process conditions. Interface properties are observed by transmission electron microscopy. Primarily results show NiAlN's suitability for use as gate material in a CMOS replacement gate technology. Fabrication of n-type metal-oxide-semiconductor field effect transistors with a MAIN gates activated at 900 degreesC is demonstrated.
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| 4. |
- Gottlob, H. D. B., et al.
(författare)
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0.86-nm CET gate stacks with epitaxial Gd2O3 high-k dielectrics and FUSINiSi metal electrodes
- 2006
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Ingår i: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 27:10, s. 814-816
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Tidskriftsartikel (refereegranskat)abstract
- In this letter, ultrathin gadolinium oxide (Gd2O3) high-kappa gate dielectrics with complementary-metal-oxide-semiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a Gd2O3 thickness of 3.1 nm yield a capacitance equivalent oxide thickness of CET = 0.86 nm. The extracted dielectric constant is kappa =-13-14. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond.
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| 5. |
- Gottlob, H. D. B., et al.
(författare)
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CMOS integration of epitaxial Gd(2)O(3) high-k gate dielectrics
- 2006
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 50:6, s. 979-985
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Tidskriftsartikel (refereegranskat)abstract
- Epitaxial gadolinium oxide (Gd(2)O(3)) high-k dielectrics are investigated with respect to their CMOS compatibility in metal oxide semiconductor (MOS) capacitors and field effect transistors (MOSFETs). MOS capacitors with various gate electrodes are exposed to typical CMOS process steps and evaluated with capacitance voltage (CV) and current voltage (JV) measurements. The effects of high temperature processes on thermal stabilities of channel/dielectric and dielectric/gate electrode interfaces is studied in detail. A feasible CMOS process with epitaxial gate oxides and metal gate electrodes is identified and demonstrated by a fully functional n-MOSFET for the first time.
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| 6. |
- Gottlob, H. D. B., et al.
(författare)
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Gd silicate : A high-k dielectric compatible with high temperature annealing
- 2009
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Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567 .- 2166-2754 .- 2166-2746. ; 27:1, s. 249-252
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Tidskriftsartikel (refereegranskat)abstract
- The authors report on the investigation of amorphous Gd-based silicates as high-k dielectrics. Two different stacks of amorphous gadolinium oxide (Gd(2)O(3)) and silicon oxide (SiO(2)) on silicon substrates are compared after annealing at temperatures up to 1000 degrees C. Subsequently formed metal oxide semiconductor capacitors show a significant reduction in the capacitance equivalent thicknesses after annealing. Transmission electron microscopy, medium energy ion scattering, and x-ray diffraction analysis reveal distinct structural changes such as consumption of the SiO(2) layer and formation of amorphous Gd silicate. The controlled formation of Gd silicates in this work indicates a route toward high-k dielectrics compatible with conventional, gate first complementary metal-oxide semiconductor integration schemes.
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| 7. |
- Gottlob, H. D. B., et al.
(författare)
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Gentle FUSI NiSi metal gate process for high-k dielectric screening
- 2008
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 85:10, s. 2019-2021
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, a process flow well suited for screening of novel high-k dielectrics is presented. In vacuo silicon capping of the dielectrics excludes process and handling induced influences especially if hygroscopic materials are investigated. A gentle, low thermal budget process is demonstrated to form metal gate electrodes by turning the silicon capping into a fully silicided nickel silicide. This process enables the investigation of rare earth oxide based high-k dielectrics and specifically their intrinsic material properties using metal oxide semiconductor (MOS) capacitors. We demonstrate the formation of nickel monosilicide electrodes which show smooth interfaces to the lanthanum- and gadolinium-based high-k oxide films. The dielectrics have equivalent oxide thicknesses of EOT = 0.95 nm (lanthanum silicate) and EOT = 0.6 nm (epitaxial gadolinium oxide).
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| 8. |
- Gottlob, H. D. B., et al.
(författare)
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Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics
- 2009
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 86:7-9, s. 1642-1645
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Tidskriftsartikel (refereegranskat)abstract
- We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high-k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd2O3) from a silicon oxide (SiO2) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). (C) 2009 Elsevier B.V. All rights reserved.
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| 9. |
- Hurley, P. K., et al.
(författare)
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Interface defects in HfO2, LaSiOx, and Gd2O3 high-k/metal-gate structures on silicon
- 2008
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Ingår i: Journal of the Electrochemical Society. - : The Electrochemical Society. - 0013-4651 .- 1945-7111. ; 155:2, s. G13-G20
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Tidskriftsartikel (refereegranskat)abstract
- In this work, we present experimental results examining the energy distribution of the relatively high (> 1 X 10(11) cm(-2)) electrically active interface defects which are commonly observed in high-dielectric-constant (high-k) metal-insulator-silicon systems during high-k process development. This paper extends previous studies on the Si(100)/SiOx/HfO2 system to include a comparative analysis of the density and energy distribution of interface defects for HfO2, lanthanum silicate (LaSiOx), and Gd2O3 thin films on (100) orientation silicon formed by a range of deposition techniques. The analysis of the interface defect density across the energy gap, for samples which experience no H-2/N-2 annealing following the gate stack formation, reveals a peak density (similar to 2 X 10(12) cm(-2) eV(-1) to similar to 1 X 10(13) cm(-2) eV(-1)) at 0.83-0.92 eV above the silicon valence bandedge for the HfO2, LaSiOx, and Gd2O3 thin films on Si (100). The characteristic peak in the interface state density (0.83-0.92 eV) is obtained for samples where no interface silicon oxide layer is observed from transmission electron microscopy. Analysis suggests silicon dangling bond (P-bo) centers as the common origin for the dominant interface defects for the various Si(100)/SiOx/high-k/metal gate systems. The results of forming gas (H-2/N-2) annealing over the temperature range 350-555 degrees C are presented and indicate interface state density reduction, as expected for silicon dangling bond centers. The technological relevance of the results is discussed. (c) 2007 The Electrochemical Society.
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| 10. |
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