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Träfflista för sökning "WFRF:(Grajal J.) "

Sökning: WFRF:(Grajal J.)

  • Resultat 1-4 av 4
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1.
  • Garcia, Angel, 1984, et al. (författare)
  • Adaptive unscented Gaussian likelihood approximation filter
  • 2015
  • Ingår i: Automatica. - : Elsevier BV. - 0005-1098. ; 54, s. 166-175
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper focuses on the update step of Bayesian nonlinear filtering. We first derive the unscented Gaussian likelihood approximation filter (UGLAF), which provides a Gaussian approximation to the likelihood by applying the unscented transformation to the inverse of the measurement function. The UGLAF approximation is accurate in the cases where the unscented Kalman filter (UKF) is not and the other way round. As a result, we propose the adaptive UGLAF (AUGLAF), which selects the best approximation to the posterior (UKF or UGLAF) based on the Kullback-Leibler divergence. This enables AUGLAF to outperform both the UKF and UGLAF.
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2.
  • Garrido Gálvez, Mario, et al. (författare)
  • Continuous-flow variable-length memoryless linear regression architecture
  • 2013
  • Ingår i: Electronics Letters. - : Institution of Engineering and Technology (IET). - 0013-5194 .- 1350-911X. ; 49:24, s. 1567-1568
  • Tidskriftsartikel (refereegranskat)abstract
    • A pipelined circuit to calculate linear regression is presented. The proposed circuit has the advantages that it can process a continuous flow of data, it does not need memory to store the input samples and supports variable length that can be reconfigured in run time. The circuit is efficient in area, as it consists of a small number of adders, multipliers and dividers. These features make it very suitable for real-time applications, as well as for calculating the linear regression of a large number of samples.
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3.
  • Garrido Gálvez, Mario, et al. (författare)
  • Pipelined Radix-2(k) Feedforward FFT Architectures
  • 2013
  • Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1063-8210 .- 1557-9999. ; 21:1, s. 23-32
  • Tidskriftsartikel (refereegranskat)abstract
    • The appearance of radix-2(2) was a milestone in the design of pipelined FFT hardware architectures. Later, radix-2(2) was extended to radix-2(k). However, radix-2(k) was only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2(k) feedforward (MDC) FFT architectures. In feedforward architectures radix-2(k) canbe used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which makes them suitable for the most demanding applications. Indeed, the proposed radix-2(k) feedforward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. As a result, the proposed radix-2(k) feedforward architectures not only offer an attractive solution for current applications, but also open up a new research line on feedforward structures.
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4.
  • Garrido, Mario, 1981-, et al. (författare)
  • Efficient Memoryless Cordic for FFT Computation
  • 2007
  • Ingår i: Efficient Memoryless Cordic for FFT Computation. - : IEEE. - 1424407281 - 1424407273 ; , s. II-113-II-116
  • Konferensbidrag (refereegranskat)abstract
    • A new memoryless CORDIC algorithm for the FFT computation is proposed in this paper. This approach calculates the direction of the micro-rotations from the control counter of the FFT, so the area of the rotator hardly depends on the number of rotations, which is particularly suitable for the computation of FFTs of a high number of points. Moreover, the new CORDIC presents other advantages such as the simplification of the basic CORDIC processor used to calculate the micro-rotations, or an easy way to compensate the intrinsic gain of the CORDIC algorithm. Additionally, the VLSI implementation of the algorithm is a pipeline architecture with high performance in terms of speed, throughput and latency.
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  • Resultat 1-4 av 4

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