| 1. |
- Baghaei Nejad, Majid, 1974-
(författare)
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Ultra Wideband Impulse Radio for Wireless Sensing and Identification
- 2008
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Ubiquitous computing and Internet-of-Things (IoT) implies an untapped opportunity in the realm of information and communication technology, in which a large number of micro-devices with communication and/or computing capabilities, provides connectivity for anything, by anyone at anytime and anywhere. Especially, these devices can be equipped with sensors and actuators that interact with our living environment. Barcode, smart contactless card, Radio Frequency Identification (RFID) systems, wireless sensor network (WSN), and smart mobile phones are some examples which can be utilized in ubiquitous computing. RFIDs and WSN have been recognized as the two promising enablers for realization of ubiquitous computing. They have some great features such as low-cost and small- size implementation, non-line of sight operation, sensing possibilities, data storing ability, and positioning. However, there are several challenges which need to be addressed, such as limited life time for battery powered device, maintenance cost, longer operation range, higher data rate, and operation in dense multipath and multiuser environment. Ultra-Wideband Impulse Radio (UWB-IR) with its huge advantages has been recognized as a great solution for future WSN and RFID. UWB-IR technique has the possibility of achieving Gb/s data rate, hundreds of meter operation range, pJ energy per bit, centimeter accuracy of positioning, and low cost implementation. In this work utilization of UWB-IR in WSN and RFID is investigated. A wireless sensor network based on UWB-IR is proposed focusing on low-cost and low-power implementation. Our contribution is to imply two different architectures in base station and sensor nodes to satisfy power, complexity and cost constraints. For sensor nodes, an autonomous UWB-IR detection is proposed, which detects the UWB signal autonomously and no restrict synchronization is required. It reduces the circuit complexity significantly. The performance in term of bit-error-rate is compared with two other common detection techniques. It is shown that the new detection is more robustness to timing jitter and clock skew, which consequently reduces the clock and synchronization requirements considerably. A novel wireless sensing and identification system, based on remote-powered tag with asymmetric wireless link, is proposed. Our innovative contribution is to deploy two different UWB and UHF communication techniques in uplink and downlink respectively. In the proposed system, tags capture the required power supply from different environmental sources (e.g. electromagnetic wave transmitted by a reader) and transmit data through an ultra-low power impulse UWB link. A new communication protocol is devised based on slotted-aloha anti-collision algorithm. By introducing several improvements including of pipelined communication, adaptive frame size, and skipping idle slots, the system throughput of more than 2000 tags/s is achieved. To prove the system concept a single chip integrated tag is implemented in UMC 0.18μm CMOS process. The measurement results show the minimum sensitivity of -18.5 dB (14.1 μW) and adaptive data rate up to 10 Mb/s. It corresponds to 13.9 meters operation range, considering 4W EIRP, a matched antenna to the tag with 0dB gain, and free space path loss. This is a great improvement in operation range and data rate, compared with conventional passive RFID, which data rate is limited to a few hundreds of Kb/s. System integration in a Liquid-Crystal-polymer (LCP) substrate is investigated. The integration of a tunable UWB-IR transmitter and a power scavenging unit are studied. Our contribution includes embedding and modeling the RF components and antenna in substrate and co-optimizing the chip and package with on-chip versus off-chip passives trade-offs. Simulation results verify the potential of system-on-package solution for UWB integration. The effect of antenna miniaturization in a UWB system is studied. Our focus is to scale down a UWB antenna and optimize the performance through the chip-antenna co-design. A tunable impulse- UWB transmitter is designed in two cases - a conventional 50Ω design and a co-design methodology. The simulation results show that the standard 50Ω design technique can not reach the best condition in all cases, when a real antenna is placed into the system. The performance can be improved significantly when doing codesign. The antennas and UWB transmitter performances are evaluated in a given UWB systems. It is shown that the operation distance at a target performance is reduced with antenna scaling factor and it can be compensated by antenna-transceiver co-design. The result proves the importance of antenna-transceiver codesign, which needs to be addressed in the earliest phases of the design flow.
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| 2. |
- Chouhan, Shailesh, et al.
(författare)
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A 352nW, 30 ppm/°C all MOS nano ampere current reference circuit
- 2017
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Ingår i: Microelectronics Journal. - : Elsevier. - 0959-8324 .- 0026-2692. ; 69, s. 45-52
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Tidskriftsartikel (refereegranskat)abstract
- In this work, an ultra low power all-MOSFET based current reference circuit, developed in 0.18 µm CMOS technology, is presented. The proposed circuit is based on the classical resistor-less beta multiplier circuit with an additional temperature compensation feature. The circuit is capable of providing the reference current in a nanoampere range for the supply voltage ranging from 1 V to 2 V in the industrial temperature range of −40 °C to 85 °C. The measurements were performed on 10 prototypes. The measured mean value of the reference current is 58.7 nA with a mean temperature coefficient value of 30 ppm/°C. In addition, the measured mean line regulation is 3.4%/V in the given supply voltage range. The total current consumption of the circuit is 352 nA and the chip area is 0.036 mm2.
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| 3. |
- Chouhan, Shailesh Singh, et al.
(författare)
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A 40 nW CMOS-Based Temperature Sensor with Calibration Free Inaccuracy within ±0.6 ◦C
- 2019
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Ingår i: Electronics. - : MDPI. - 2079-9292. ; 8:11
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Tidskriftsartikel (refereegranskat)abstract
- In this study, a temperature equivalent voltage signal was obtained by subtracting output voltages received from two individual temperature sensors. These sensors work in the subthreshold region and generate the output voltage signals that are proportional and complementary to the temperature. Over the temperature range of −40 ∘" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">∘C to +85 ∘" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">∘C without using any calibration method, absolute temperature inaccuracy less than ±0.6 ∘" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">∘C was attained from the measurement of five prototypes of the proposed temperature sensor. The implementation was done in a standard 0.18 μ" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">μ m CMOS technology with a total area of 0.0018 mm 2" role="presentation" style="box-sizing: border-box; max-height: none; display: inline; line-height: normal; word-spacing: normal; overflow-wrap: normal; white-space: nowrap; float: none; direction: ltr; max-width: none; min-width: 0px; min-height: 0px; border: 0px; padding: 0px; margin: 0px; position: relative;">2. The total power consumption is 40 nW for a supply voltage of 1.2 V measured at room temperature.
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| 4. |
- Chouhan, Shailesh Sing, et al.
(författare)
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Ultra low power beta multiplier-based current reference circuit
- 2017
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Ingår i: Analog Integrated Circuits and Signal Processing. - : Springer. - 0925-1030 .- 1573-1979. ; 93:3, s. 523-529
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Tidskriftsartikel (refereegranskat)abstract
- This work presents a current reference circuit fabricated in a standard 0.18 μm CMOS technology. The reference current is obtained by applying thermal compensation voltage in the conventional self-biased or beta multiplier-based current reference circuit. Eight prototypes of the proposed architecture were measured which have resulted into the mean reference current of 26.1 nA with the temperature coefficient of 202.1 ppm/°C. These measurements were performed in the temperature range of − 40 to + 85 °C. The circuit is capable of working over the supply voltage range of 1–2 V with the measured mean line sensitivity of 2.18%/V. The maximum measured power dissipation of the circuit is 104 nW at 2 V.
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| 5. |
- Duo, Xinzhong
(författare)
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System-on-package solutions for multi-band RF front end
- 2005
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Advances in microelectronics technology have enabled us to integrate a complex electronic system (such as a radio) on a single chip or in a single package module, known as system-on-chip (SoC) and system-on-package (SoP) paradigms. This brings not only new opportunities for system integration, but also challenges in design and implementation. One of these challenges is how to achieve an optimum total solution of system integration via chip and package co-design, because there is no tool or design methodology available for such kind of optimization. This thesis focuses on innovative multi-band multi-standard radio front-end design and explores a new design methodology. The motivation of developing this design methodology is to achieve an optimum total solution for radio system implementation via chip and package co-design and co-optimization. The methodology starts from RF packaging and components modeling. Necessary models for both on-chip and off-chip passives are developed. Parasitic effects of packages for radio chips are modeled for particular frequencies. Compared with high-speed digital packaging, RF packaging normally deals with narrow band signals. It is possible to absorb some unwanted parasitics by designing proper port matching networks. In addition, cost-performance trade-offs are performed. In this context, we first developed process and technology based cost models, which include parameters like chip real estate, raw materials, package, test and rework. Impact of process variation on final yield has also been considered in the models by using a statistical analysis approach. Performance of different design options is measured by a special FoM (figure-of-merit). Each type of analog/RF circuit (such as LNA, PA and ADC) has its own dedicated FoM. Through a series of cost-performance trade-offs for different on-chip versus off-chip passives and partitions, an optimum total solution is obtained. Finally, this methodology was demonstrated via a number of design examples for multi-band multi-standard radio front-end. The author has explored the optimum solutions for different circuit architectures and process technologies encompassing parallel, concurrent and digitally programmable multi-band radio frond-end blocks. It is interesting to find that, for complex RF circuits like a multi-band multi-standard radio, moving some passives off-chip will have significant cost-savings. In addition to the above contributions, the author has also developed an MCM-D technology on LCP and glass substrates, based on metal deposition and BCB spin-coating at KTH clean room. The author has also performed some preliminary studies on UWB radio for RFID applications.
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| 6. |
- Nunez-Prieto, Ricardo, et al.
(författare)
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A Real-Time Gesture Recognition System with FPGA Accelerated ZynqNet Classification
- 2019
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Ingår i: 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019 : NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings - NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings. - 9781728127699 - 9781728127705
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Konferensbidrag (refereegranskat)abstract
- This paper presents a real-time hand gesture recognition system by accelerating a convolutional neural network (CNN) using FPGA platform. More specifically, ZynqNet is adopted and modified to fulfill the classification task of recognizing the Swedish manual alphabet, which is used by sign language users for spelling purposes, also known as fingerspelling. Data augmentation and transfer learning techniques have been used during the training phase to improve the classification accuracy up to 80.1%, even with an 8-bit ZynqNet model. Extensive analysis of memory requirements and data processing patterns has been performed to enable optimization techniques, including memory partitioning and register arrays. The resulting FPGA implementation on a Xilinx UltraScale device avoids the use of off-chip memories, which together with block-wise processing scheduling, achieves an image rate of 23.5 frames per second (FPS) at 200 MHz clock frequency.
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| 7. |
- Qin, Yajie, 1979-
(författare)
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Low Power Analog Interface Circuits toward Software Defined Sensors
- 2016
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Internet of Things is expanding to the areas such as healthcare, home management, industrial, agriculture, and becoming pervasive in our life, resulting in improved efficiency, accuracy and economic benefits. Smart sensors with embedded interfacing integrated circuits (ICs) are important enablers, hence, variety of smart sensors are required. However, each type of sensor requires specific interfacing chips, which divides the huge market of sensors’ interface chips into lots of niche markets, resulting in high develop cost and long time-to-market period for each type. Software defined sensor is regarded as a promising solution, which is expected to use a flexible interface platform to cover different sensors, deliver specificity through software programming, and integrate easily into the Internet of Things. In this work, research is carried out on the design and implementations of ultra low power analog interface circuits toward software defined sensors for healthcare services based on Internet of Things. This thesis first explores architectures and circuit techniques for energy-efficient and flexible analog to digital conversion. A time-spreading digital calibration, to calibrate the errors due to finite gain and capacitor mismatch in multi-bit/stage pipelined converters, is developed with short convergence time. The effectiveness of the proposed technique is demonstrated with intensive simulations. Two novel circuit level techniques, which can be combined with digital calibration techniques to further improve the energy efficiency of the converters, are also presented. One is the Common-Mode-Sensing-and-Input-Interchanging (CSII) operational-transconductance-amplifier (OTA) sharing technique to enable eliminating potential memory effects. The other is a workload-balanced multiplying digital-to-analog converter (MDAC) architecture to improve the settling efficiency of a high linear multi-bit stage. Two prototype converters have been designed and fabricated in 0.13 μm CMOS technology. The first one is a 14 bit 50 MS/s digital calibrated pipelined analog to digital converter that employs the workload-balanced MDAC architecture and time-spreading digital calibration technique to achieve improved power-linearity tradeoff. The second one is a 1.2 V 12 bit 5~45 MS/s speed and power-scalable ADC incorporating the CSII OTA-sharing technique, sample-and-hold-amplifier-free topology and adjustable current bias of the building blocks to minimize the power consumption. The detailed measurement results of both converters are reported and deliver the experimental verification of the proposed techniques. Secondly, this research investigates ultra-low-power analog front-end circuits providing programmability and being suitable for different types of sensors. A pulse-width- -modulation-based architecture with a folded reference is proposed and proven in a 0.18 μm technology to achieve high sensitivity and enlarged dynamic range when sensing the weak current signals. A 8-channel bio-electric sensing front-end, fabricated in a 0.35 μm CMOS technology is also presented that achieves an input impedance of 1 GΩ, input referred noise of 0.97 Vrms and common mode rejection ratio of 114 dB. With the programmable gain and cut-off frequency, the front-end can be configured to monitor for long-term a variety of bio-electric signals, such as electrooculogram (EOG), electromyogram (EMG), electroencephalogram (EEG) and electrocardiogram (ECG) signals. The proposed front-end is integrated with dry electrodes, a microprocessor and wireless link to build a battery powered E-patch for long-term and continuous monitoring. In-vivo test results with dry electrodes in the field trials of sitting, standing, walking and running slowly, show that the quality of ECG signal sensed by the E-patch satisfies the requirements for preventive cardiac care. Finally, a wireless multimodal bio-electric sensor system is presented. Enabled by a customized flexible mixed-signal system on chip (SoC), this bio-electric sensor system is able to be configured for ECG/EMG/EEG recording, bio-impedance sensing, weak current stimulation, and other promising functions with biofeedback. The customized SoC, fabricated in a 0.18 μm CMOS technology, integrates a tunable analog front-end, a 10 bit ADC, a 14 bit sigma-delta digital to current converter, a 12 bit digital to voltage converter, a digital accelerator for wavelet transformation and data compression, and a serial communication protocol. Measurement results indicate that the SoC could support the versatile bio-electric sensor to operate in various applications according to specific requirements.
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| 8. |
- Ramzan, Rashad, 1971-
(författare)
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Flexible Wireless Receivers: On-Chip Testing Techniques and Design for Testability
- 2009
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- In recent years the interest in the design of low cost multistandard mobile devices has gone from technical aspiration to the commercial reality. Usually, the emerging wireless applications prompt the conception of new wireless standards. The end user wants to access voice, data, and streaming media using a single wireless terminal. In RF perspective, these standards differ in frequency band, sensitivity, data rate, bandwidth, and modulation type. Therefore, a flexible multistandard radio receiver covering most of the cellular, WLAN, and short range communication standards in 800MHz to 6GHz band is highly desired. To keep the cost low, high level of integration becomes a necessity for the multistandard flexible radio.Due to aggressive CMOS scaling the fT of the transistors has surpassed the value of 200 GHz. Moreover, as the CMOS technology has proven to be the best suited for monolithic integration, therefore it seems to be the future choice for the physical implementation of such a flexible receiver. In this thesis, two multiband sampling radio receiver front-ends implemented in 130 nm and 90 nm CMOS including test circuitry (DfT) are presented that is one step ahead in this direction.In modern radio transceivers the estimated cost of testing is a significant portion of manufacturing cost and is escalating with every new generation of RF chips. In order to reduce the test cost it is important to identify the faulty circuits very early in the design flow, even before packaging. In this thesis, on-chip testing techniques to reduce the test time and cost are presented. For integrated RF transceivers the chip reconfiguration by loopback setup can be used. Variants including the bypassing technique to improve testability and to enable on-chip test when the direct loopback is not feasible are presented. A technique for boosting the testability by the elevated symbol error rate test (SER) is also presented. It achieves better sensitivity and shorter test time compared to the standard SER test.Practical DfT implementation is addressed by circuit level design of various test blocks such as a linear attenuator, stimulus generator, and RF detectors embedded in RF chips without notable performance penalty. The down side of CMOS scaling is the increase in parameter variability due to process variations and mismatch. Both the test circuitry (DfT) and the circuit under test (CUT) are affected by these variations. A new calibration scheme for the test circuitry to compensate this effect is presented. On-chip DC measurements supported by a statistical regression method are used for this purpose.Wideband low-reflection PCB transmission lines are needed to enable the functional RF testing using external signal generators for RF chips directly bonded on the PCB. Due to extremely small chip dimensions it is not possible to layout the transmission line without width discontinuity. A step change in the substrate thickness is utilized to cancel this effect thus resulting in the low-reflection transmission line.In summary, all of these techniques at the system and circuit level pave a way to new opportunities towards low-cost transceiver testing, especially in volume production.
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| 9. |
- Tan, Siyu, et al.
(författare)
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A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS
- 2019
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Ingår i: 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019 : NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings - NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings. - 9781728127705 - 9781728127699
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Konferensbidrag (refereegranskat)abstract
- This paper presents a continuous-time ΔΣ ADC in a 28nm-FDSOI CMOS technology. The ADC is clocked at 5GHz with a signal bandwidth of 250 MHz, for an oversampling ratio (OSR) of only 10. The conversion from high-level model to circuit-level implementation requires multiple high-speed design methodologies and a careful layout. A 4th order loop filter is adopted to enhance quantization noise shaping in presence of a low OSR. The loop filter is built with inverter-based integrators, and the transistors are tuned by adjusting body-biasing voltages. The extra loop delay exceeds one clock cycle, requiring two additional feedback paths to restore the nominal noise transfer function. Furthermore, current-mode logic is used in the digital part to improve the signal transition speed. The ΔΣ ADC has a simulated SNDR of 73.1 dB for a simulated power consumption of 232mW.
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| 10. |
- Zhou, Qin, 1984-
(författare)
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Sub-Nyquist Sampling Impulse Radio UWB Receivers for the Internet-of-Things
- 2016
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- In the era of Internet-of-Things, the demand for short range wireless links featured by low-power and low-cost, robust communication and high-precision positioning is growing rapidly. Impulse Radio Ultra-Wideband (IR-UWB) technology characterized by the transmission of sub-nanosecond pulses spanning up to several GHz band with extremely low power spectral density emerges as a promising candidate. Nevertheless, several challenges must be confronted in order to take the full advantage of IR-UWB technology. The most significant one lies in the reception of UWB signals. Traditional receiver requires Nyquist rate ADC which is overwhelmingly complex and power hungry. This dissertation proposes and investigates possible sub-Nyquist sampling techniques for IR-UWB receiver design.In the first part of this dissertation, the IR-UWB receiver based on energy detection (ED) principle is explored. A low-power ED receiver featured by flexibility and multi-mode operation is proposed. The receiver prototype for 3-5 GHz band is implemented in 90 nm CMOS. Measurement results demonstrate that 16.3 mW power consumption and -79 dBm sensitivity at 10 Mb/s data rate can be achieved. To further optimize the receiver performance, threshold optimization is suggested for the on-off-keying modulated signal, and adaptive synchronization and integration region optimization is proposed. Finally, a low complexity burst packet detection scheme is proposed, which is adaptive to the variations of noise background and link distance.In the second part of this dissertation, the IR-UWB receiver based on compressed sensing (CS) theory is investigated. Firstly, appropriate sparse basis, sensing matrix and reconstruction algorithms are suggested for the CS based IR-UWB receiver. And then, the architectural analysis of the CS receiver with focuses on the random noise processes in the CS measurement procedure is presented. At last, a novel two-path noise-reducing architecture for the CS receiver is proposed. Besides the improvement on the receiver performance, the proposed architecture also relaxes the hardware implementation of the CS random projection as well as the back-end signal reconstruction.
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