| 1. |
- Fan, Qunping, 1989, et al.
(författare)
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Mechanically Robust All-Polymer Solar Cells from Narrow Band Gap Acceptors with Hetero-Bridging Atoms
- 2020
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Ingår i: Joule. - : Elsevier BV. - 2542-4351. ; 4:3, s. 658-672
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Tidskriftsartikel (refereegranskat)abstract
- We developed three narrow band-gap polymer acceptors PF2-DTC, PF2-DTSi, and PF2-DTGe with different bridging atoms (i.e., C, Si, and Ge). Studies found that such different bridging atoms significantly affect the crystallinity, extinction coefficient, electron mobility of the polymer acceptors, and the morphology and mechanical robustness of related active layers. In all-polymer solar cells (all-PSCs), these polymer acceptors achieved high power conversion efficiencies (PCEs) over 8.0%, while PF2-DTSi obtained the highest PCE of 10.77% due to its improved exciton dissociation, charge transport, and optimized morphology. Moreover, the PF2-DTSi-based active layer showed excellent mechanical robustness with a high toughness value of 9.3 MJ m−3 and a large elongation at a break of 8.6%, which is a great advantage for the practical applications of flexible devices. As a result, the PF2-DTSi-based flexible all-PSC retained >90% of its initial PCE (6.37%) after bending and relaxing 1,200 times at a bending radius of ∼4 mm.
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| 2. |
- Radamson, Henry H., et al.
(författare)
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Miniaturization of CMOS
- 2019
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Ingår i: Micromachines. - : MDPI AG. - 2072-666X. ; 10:5
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Tidskriftsartikel (refereegranskat)abstract
- When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today's 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.
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| 3. |
- Radamson, Henry H., et al.
(författare)
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State of the Art and Future Perspectives in Advanced CMOS Technology
- 2020
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Ingår i: Nanomaterials. - : MDPI AG. - 2079-4991. ; 10:8
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Forskningsöversikt (refereegranskat)abstract
- The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.
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| 4. |
- Radamson, Henry H., et al.
(författare)
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The Challenges of Advanced CMOS Process from 2D to 3D
- 2017
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Ingår i: Applied Sciences. - : MDPI AG. - 2076-3417. ; 7:10
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Forskningsöversikt (refereegranskat)abstract
- The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.
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