| 1. |
- Berg, Martin, et al.
(författare)
-
Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si
- 2016
-
Ingår i: IEEE Electron Device Letters. - 0741-3106. ; 37:8, s. 966-969
-
Tidskriftsartikel (refereegranskat)abstract
- Vertical InAs nanowire transistors are fabricated on Si using a gate-last method, allowing for lithography-based control of the vertical gate length. The best devices combine good ON- and OFF-performance, exhibiting an ON-current of 0.14 mA/μm, and a sub-threshold swing of 90 mV/dec at 190 nm LG. The device with the highest transconductance shows a peak value of 1.6 mS/μm. From RF measurements, the border trap densities are calculated and compared between devices fabricated using the gate-last and gate-first approaches, demonstrating no significant difference in trap densities. The results thus confirm the usefulness of implementing digital etching in thinning down the channel dimensions.
|
|
| 2. |
- Gaggio, Benedetta, et al.
(författare)
-
Sodium-Controlled Interfacial Resistive Switching in Thin Film Niobium Oxide for Neuromorphic Applications
- 2024
-
Ingår i: Chemistry of Materials. - : AMER CHEMICAL SOC. - 0897-4756 .- 1520-5002.
-
Tidskriftsartikel (refereegranskat)abstract
- A double layer 2-terminal device is employed to show Na-controlled interfacial resistive switching and neuromorphic behavior. The bilayer is based on interfacing biocompatible NaNbO3 and Nb2O5, which allows the reversible uptake of Na+ in the Nb2O5 layer. We demonstrate voltage-controlled interfacial barrier tuning via Na+ transfer, enabling conductivity modulation and spike-amplitude- and spike-timing-dependent plasticity. The neuromorphic behavior controlled by Na+ ion dynamics in biocompatible materials shows potential for future low-power sensing electronics and smart wearables with local processing.
|
|
| 3. |
- Hellenbrand, Markus, et al.
(författare)
-
Capacitance Measurements in Vertical III-V Nanowire TFETs
- 2018
-
Ingår i: IEEE Electron Device Letters. - 0741-3106. ; 39:7, s. 943-946
-
Tidskriftsartikel (refereegranskat)abstract
- By measuring scattering parameters over a wide range of bias points, we study the intrinsic gate capacitance as well as the charge partitioning of vertical nanowire tunnel field-effect transistors (TFETs). The gate-to-drain capacitance Cgd is found to largely dominate the on-state of TFETs, whereas the gate-to-source capacitance Cgs is sufficiently small to be completely dominated by parasitic components. This indicates that the tunnel junction on the source side almost completely decouples the channel charge from the small-signal variation in the source, while the absence of a tunnel junction on the drain side allows the channel charge to follow the drain small-signal variation much more directly.
|
|
| 4. |
- Hellenbrand, Markus, et al.
(författare)
-
Comparison of Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
- 2019
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- We compare III-V nanowire (NW) metal-oxidesemiconductor field-effect transistors (MOSFETs) in a vertical gate-all-around (GAA) as well as a lateral trigate architecture with planar reference MOSFETs and reveal that the NW geometry does not deteriorate the low-frequency noise (LFN) performance. In fact, with gate oxides deposited at the same conditions, the NW structures show potential to achieve better metrics due to slightly lower border trap densities Nbt. The normalized LFN in transistors with a higher number of NW can degrade due to averaging effects between individual nanowires within the same device.
|
|
| 5. |
- Hellenbrand, Markus, et al.
(författare)
-
Effect of Gate Oxide Defects on Tunnel Transistor RF Performance
- 2018
-
Ingår i: 2018 76th Device Research Conference (DRC). - 9781538630280 ; , s. 137-138
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Tunnel field-effect transistors (TFETs) are designed for low off-state leakage and low drive voltages. To investigate how capable TFETs are of RF operation, we measured their scattering parameters and performed small-signal modeling. We find that in the low frequency ranges, gate oxide defects have a major influence on the RF performance of these devices, which can be modeled by a frequency-dependent gate-to-drain conductance ggd;w. This model is based on charge trapping in gate oxide defects and was studied before for metal-oxide-semiconductor capacitors.
|
|
| 6. |
- Hellenbrand, Markus, et al.
(författare)
-
Effects of traps in the gate stack on the small-signal RF response of III-V nanowire MOSFETs
- 2020
-
Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101. ; 171
-
Tidskriftsartikel (refereegranskat)abstract
- We present a detailed study of the effect of gate-oxide-related defects (traps) on the small-signal radio frequency (RF) response of III-V nanowire MOSFETs and find that the effects are clearly identifiable in the measured admittance parameters and in important design parameters such as h21 (forward current gain) and MSG (maximum stable gain). We include the identified effects in a small-signal model alongside results from previous investigations of III-V RF MOSFETs and thus provide a comprehensive physical small-signal RF model for this type of transistor, which accurately describes the measured admittance parameters and gains. We verify the physical basis of the model assumptions by calculating the oxide defect density from the measured admittances.
|
|
| 7. |
- Hellenbrand, Markus
(författare)
-
Electrical Characterisation of III-V Nanowire MOSFETs
- 2020
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The ever increasing demand for faster and more energy-efficient electricalcomputation and communication presents severe challenges for the semiconductor industry and particularly for the metal-oxidesemiconductorfield-effect transistor (MOSFET), which is the workhorse of modern electronics. III-V materials exhibit higher carrier mobilities than the most commonly used MOSFET material Si so that the realisation of III-V MOSFETs can enable higher operation speeds and lower drive voltages than that which is possible in Si electronics. A lowering of the transistor drive voltage can be further facilitated by employing gate-all-around nanowire geometries or novel operation principles. However, III-V materials bring about their own challenges related to material quality and to the quality of the gate oxide on top of a III-V MOSFET channel.This thesis presents detailed electrical characterisations of two types of (vertical) III-V nanowire transistors: MOSFETs based on conventional thermionic emission; and Tunnel FETs, which utilise quantum-mechanical tunnelling instead to control the device current and reach inverse subthreshold slopes below the thermal limit of 60 mV/decade. Transistor characterisations span over fourteen orders of magnitude in frequency/time constants and temperatures from 11 K to 370 K.The first part of the thesis focusses on the characterisation of electrically active material defects (‘traps’) related to the gate stack. Low-frequency noise measurements yielded border trap densities of 10^18 to 10^20 cm^-3 eV^-1 and hysteresis measurements yielded effective trap densities – projected to theoxide/semiconductor interface – of 2x10^12 to 3x10^13 cm^-2 eV^-1. Random telegraph noise measurements revealed that individual oxide traps can locally shift the channel energy bands by a few millielectronvolts and that such defects can be located at energies from inside the semiconductor band gap all the way into the conduction band.Small-signal radio frequency (RF) measurements revealed that parts of the wide oxide trap distribution can still interact with carriers in the MOSFET channel at gigahertz frequencies. This causes frequency hystereses in the small-signal transconductance and capacitances and can decrease the RF gains by a few decibels. A comprehensive small-signal model was developed, which takes into account these dispersions, and the model was applied to guide improvements of the physical structure of vertical RF MOSFETs. This resulted in values for the cutoff frequency fT and the maximum oscillation frequency fmax of about 150 GHz in vertical III-V nanowire MOSFETs.Bias temperature instability measurements and the integration of (lateral) III-V nanowire MOSFETs in a back end of line process were carried out as complements to the main focus of this thesis. The results of this thesis provide a broad perspective of the properties of gate oxide traps and of the RF performance of III-V nanowire transistors and can act as guidelines for further improvement and finally the integration of III-V nanowire MOSFETs in circuits.
|
|
| 8. |
- Hellenbrand, Markus, et al.
(författare)
-
Low-Frequency Noise in III-V Nanowire TFETs and MOSFETs
- 2017
-
Ingår i: IEEE Electron Device Letters. - 0741-3106.
-
Tidskriftsartikel (refereegranskat)abstract
- We present a detailed analysis of low-frequency noise (LFN) measurements in vertical III-V nanowire tunnel fieldeffect transistors (TFETs), which helps to understand the limiting factors of TFET operation. A comparison with LFN in vertical metal-oxide semiconductor field-effect transistors with the same channel material and gate oxide shows that the LFN in these TFETs is dominated by the gate oxide properties, which allowed us to optimize the TFET tunnel junction without deteriorating the noise performance. By carefully selecting the TFET heterostructure materials, we reduced the inverse subthreshold slope well below 60 mV/decade for a constant LFN level.
|
|
| 9. |
- Hellenbrand, Markus, et al.
(författare)
-
Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
- 2019
-
Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317.
-
Tidskriftsartikel (refereegranskat)abstract
- Nanowire geometries are leading contenders for future low-power transistor design. In this study, low-frequency noise is measured and evaluated in highly scaled III-V nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) and in planar III-V MOSFETs to investigate to what extent the device geometry affects the noise performance. Number fluctuations are identified as the dominant noise mechanism in both architectures. In order to perform a thorough comparison of the two architectures, a discussion of the underlying noise model is included. We find that the noise performance of the MOSFETs in a nanowire architecture is at least comparable to the planar devices. The input-referred voltage noise in the nanowire devices is superior by at least a factor of four.
|
|
| 10. |
- Hellenbrand, Markus, et al.
(författare)
-
Random telegraph signal noise in tunneling field-effect transistors with S below 60 mV/decade
- 2017
-
Ingår i: 47th European Solid-State Device Research Conference (ESSDERC), 2017. - 9781509059782 - 9781509059799 ; , s. 38-41
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Single gate oxide defects in strongly scaled Tunneling Field-Effect Transistors with an inverse subthreshold slope well below 60 mV/decade are investigated by Random Telegraph Signal (RTS) noise measurements. The cause for RTS noise are electrons being captured in and released from individual defects in the gate oxide. Under the assumption that elastic tunneling is the underlying capture and emission mechanism, the measured RTS time constants vary with the relative position of the channel Fermi level and the defect energy level while the amplitudes — independent of the capture and release mechanism — follow the inverse of the inverse subthreshold slope.
|
|
