| 1. |
- Bethge, O., et al.
(författare)
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Effective reduction of trap density at the Y2O3/Ge interface by rigorous high-temperature oxygen annealing
- 2014
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Ingår i: Journal of Applied Physics. - : AIP Publishing. - 0021-8979 .- 1089-7550. ; 116:21, s. 214111-
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Tidskriftsartikel (refereegranskat)abstract
- The impact of thermal post deposition annealing in oxygen at different temperatures on the Ge/Y2O3 interface is investigated using metal oxide semiconductor capacitors, where the yttrium oxide was grown by atomic layer deposition from tris(methylcyclopentadienyl) yttrium and H2O precursors on n-type (100)-Ge substrates. By performing in-situ X-ray photoelectron spectroscopy, the growth of GeO during the first cycles of ALD was proven and interface trap densities just below 1 x 10(11) eV(-1) cm(-2) were achieved by oxygen annealing at high temperatures (550 degrees C-600 degrees C). The good interface quality is most likely driven by the growth of interfacial GeO2 and thermally stabilizing yttrium germanate.
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| 2. |
- Bethge, O., et al.
(författare)
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Fabrication of highly ordered nanopillar arrays and defined etching of ALD-grown all-around platinum films
- 2012
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Ingår i: Journal of Micromechanics and Microengineering. - : IOP Publishing. - 0960-1317 .- 1361-6439. ; 22:8, s. 085013-
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Tidskriftsartikel (refereegranskat)abstract
- Highly ordered arrays of silicon nanopillars are etched by means of induced-coupled-plasma reactive-ion etching (RIE). The sulfur hexafluoride/oxygen (SF6/O-2)-based cryogenic process allows etching of nanopillars with an aspect ratio higher than 20:1 and diameters down to 30 nm. Diameters can be further reduced by a well-controllable oxidation process in O-2-ambient and a subsequent etching in hydrofluoric acid. This approach effectively removes surface contaminations induced by former RIE, as shown by x-ray photoelectron spectroscopy. Atomic layer deposition (ALD) is used to establish an all-around Al2O3/Pt stack onto the vertically aligned nanorods. Two approaches are successfully applied to remove the resistant Pt coating from the nanopillar tips.
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| 3. |
- Dentoni Litta, Eugenio, et al.
(författare)
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Characterization of thulium silicate interfacial layer for high-k/metal gate MOSFETs
- 2013
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Ingår i: 2013 14th International Conference On Ultimate Integration On Silicon (ULIS). - : IEEE. - 9781467348027 ; , s. 122-125
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Konferensbidrag (refereegranskat)abstract
- The possibility of integrating thulium silicate as IL (interfacial layer) in scaled high-klmetal gate stacks is explored. Electrical properties of the silicate IL are investigated in MOS capacitor structures for the silicate formation temperature range 500-900 degrees C. Results are compared to lanthanum silicate. A CMOS-compatible process flow for silicate formation is demonstrated, providing EOT of the IL as low as 0.1-0.3 nm and interface state density at flatband below 2.10(11) cm(-2)eV(-1). The silicate IL is found to be compatible with both gate-last and gate-first process flows, with a maximum thermal budget of 1000 degrees C.
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| 4. |
- Dentoni Litta, Eugenio, et al.
(författare)
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Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology
- 2014
-
Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 98, s. 20-25
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Tidskriftsartikel (refereegranskat)abstract
- This work presents a characterization of the electrical properties of thulium silicate thin films, within the scope of a possible application as IL (interfacial layer) in scaled high-k/metal gate CMOS technology. Silicate formation is investigated over a wide temperature range (500-900 degrees C) through integration in MOS capacitor structures and analysis of the resulting electrical properties. The results are compared to those obtained from equivalent devices integrating lanthanum silicate interfacial layers. The thulium silicate IL is formed through a gate-last CMOS-compatible process flow, providing IL EOT of 0.1-0.3 nm at low formation temperature and interface state density at flatband condition below 2 x 10(11) cm(-2) eV(-1). The effects of a possible integration in a gate-first process flow with a maximum thermal budget of 1000 degrees C are also evaluated, achieving an IL EOT of 0.2-0.5 nm, an interface state density at flatband condition similar to 1 x 10(11) cm(-2) eV(-1) and a reduction in gate leakage current density of one order of magnitude compared to the same stack without IL.
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| 5. |
- Dentoni Litta, Eugenio, et al.
(författare)
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High-Deposition-Rate Atomic Layer Deposition of Thulium Oxide from TmCp3 and H2O
- 2013
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Ingår i: Journal of the Electrochemical Society. - : The Electrochemical Society. - 0013-4651 .- 1945-7111. ; 160:11, s. D538-D542
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Tidskriftsartikel (refereegranskat)abstract
- A novel process for atomic layer deposition of thulium oxide (Tm2O3) has been developed, employing TmCp3 as metal precursor and H2O as oxidizing agent. The use of a highly reactive oorganometallic precursor eliminates the need for a strong oxidizing agent (such as O-3) and provides a high deposition rate of similar to 1.5 angstrom/cycle. A thorough characterization of the process has been performed, identifying true ALD-type film growth in the temperature range 200-300 degrees C. The ALD process has been further investigated by extensive physical and electrical characterization of the deposited films in terms of-composition, crystalline phase, surface roughness and extraction of the dielectric constant. The films were found to be oxygen-rich Tm2O3, with low carbon impurity content at low deposition temperature and after annealing at 600 degrees C. The developed process produced polycrystalline films, with a surface roughness <1 nm RMS. Integration in MOS capacitors demonstrated well-behaved CV curves after annealing at 600 degrees C, with a relative dielectric constant of similar to 16.
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| 6. |
- Dentoni Litta, Eugenio, et al.
(författare)
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In situ SiOx interfacial layer formation for scaled ALD high-k/metal gate stacks
- 2012
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Ingår i: 2012 13th International Conference on Ultimate Integration on Silicon, ULIS 2012. - : IEEE. - 9781467301916 ; , s. 105-108
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Konferensbidrag (refereegranskat)abstract
- This work addresses the issue of interfacial layer formation in scaled high-k/metal gate stacks: the possibility of growing a thin SiOx interfacial layer in situ in a commercial ALD reactor has been evaluated, employing ozone-based Si oxidation. Three techniques (O3, O3/H2O and Pulsed) have been developed to grow scaled sub-nm interfacial layers and have been integrated in MOS capacitors and MOSFETs. A comparison based on electrical characterization shows that the performance of the proposed in situ methods is comparable or superior to that of existing ex situ techniques; specifically, the O3 method can grow aggressively scaled interfacial layers (4-5 A) while preserving the electrical quality of the stack.
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| 7. |
- Dentoni Litta, Eugenio, et al.
(författare)
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Thulium silicate interfacial layer for scalable high-k/metal gate stacks
- 2013
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 60:10, s. 3271-3276
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Tidskriftsartikel (refereegranskat)abstract
- Interfacial layer (IL) control in high-k/metal gate stacks is crucial in achieving good interface quality, mobility, and reliability. A process is developed for the formation of a thulium silicate IL that can be integrated as a replacement for conventional chemical oxide ILs in gate-last high-k/metal gate CMOS process. A straightforward process integration scheme for thulium silicate IL is demonstrated, based on self-limiting silicate formation in inert gas atmosphere and with good selectivity of the etching step. The thulium silicate IL is shown to provide 0.25~{!@~}0.15 nm equivalent oxide thickness of the IL while preserving excellent electrical quality of the interface with Si. An interface state density ~0.7-21011 cm-2eV-1 was obtained at flat-band condition, and the nFET and pFET subthreshold slopes were 70 mV/dec. The inversion layer mobility was 20% higher than for the reference SiOx/HfO2 gate stack. Specifically, the measured mobility values were 230 cm2/ Vs for nFET and 60 cm2/Vs for pFET devices, at an inversion charge density of 1013 cm?2 and at a total capacitance equivalent thickness of 1.6 nm.
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| 8. |
- Hallén, Anders, et al.
(författare)
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Passivation of SiC device surfaces by aluminum oxide
- 2014
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Ingår i: IOP Conference Series. - 1757-8981 .- 1757-899X. ; 56:1, s. 012007-
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Tidskriftsartikel (refereegranskat)abstract
- A steady improvement in material quality and process technology has made electronic silicon carbide devices commercially available. Both rectifying and switched devices can today be purchased from several vendors. This successful SiC development over the last 25 years can also be utilized for other types of devices, such as light emitting and photovoltaic devices, however, there are still critical problems related to material properties and reliability that need to be addressed. This contribution will focus on surface passivation of SiC devices. This issue is of utmost importance for further development of SiC MOSFETs, which so far has been limited by reliability and low charge carrier surface mobilities. Also bipolar devices, such as BJTs, LEDs, or PV devices will benefit from more efficient and reliable surface passivation techniques in order to maintain long charge carrier lifetimes. Silicon carbide material enables the devices to operate at higher electric fields, higher temperatures and in more radiation dense applications than silicon devices. To be able to utilize the full potential of the SiC material, it is therefore necessary to develop passivation layers that can sustain these more demanding operation conditions. In this presentation it will also be shown that passivation layers of Al2O3 deposited by atomic layer deposition have shown superior radiation hardness properties compared to traditional SiO2-based passivation layers.
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| 9. |
- Henkel, Christoph, et al.
(författare)
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Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks
- 2011
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Ingår i: European Solid-State Device Res. Conf.. - 9781457707056 ; , s. 75-78
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Konferensbidrag (refereegranskat)abstract
- The current work is discussing the surface passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition for use in Ge-based MOSFET devices. The improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing agencies in presence of thin Pt cap layers are investigated. The results suggest the formation of thin intermixed La xGeyOz interfacial layers with thicknesses controllable by oxidation time. An additional reduction treatment further improves the electrical properties of the gate dielectrics in contact to the Ge substrate. The scaling potential of the respective layered gate dielectrics used in MOS-based device structures is discussed. As a result low interface trap densities of the ALD deposited La2O3/ZrO2 layers on (100) Ge down to 3·1011 eV-1 cm -2 are demonstrated. A trade-off between improved interface trap density and equivalent oxide thickness is found.
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| 10. |
- Henkel, Christoph, et al.
(författare)
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Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks
- 2012
-
Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 74, s. 7-12
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Tidskriftsartikel (refereegranskat)abstract
- The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed LaxGeyOz interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (100) Ge down to 3 x 10(11) eV(-1) cm(-2) are demonstrated. The formation of the high-k LaxGeyOz, layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.
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