| 1. |
- Bertilsson, Erik, 1990-, et al.
(författare)
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Low-Latency Parallel Hermitian Positive-Definite Matrix Inversion for Massive MIMO
- 2021
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Ingår i: 2021 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS 2021). - : Institute of Electrical and Electronics Engineers (IEEE). - 9781665401449 - 9781665401456 ; , s. 23-28
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Konferensbidrag (refereegranskat)abstract
- In this work, the effect of latency for three different positive definite matrix inversion algorithms when implemented on parallel and pipelined processing elements is considered. The work is motivated by the fact that in a massive MIMO system, matrix inversion needs to be performed between estimating the channels and producing the transmitted downlink signal, which means that the latency of the matrix inversion has a significant impact on the system performance. It is shown that, despite the algorithms having different complexity, all three algorithms can have the lowest latency for different number of processing elements and pipeline levels. Especially, in systems with many processing elements, the algorithm with the highest complexity has the lowest latency.
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| 2. |
- Gustafsson, Oscar, 1973-, et al.
(författare)
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Approximate Neumann Series or Exact Matrix Inversion for Massive MIMO? (Invited Paper)
- 2017
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Ingår i: Proceedings 2017 IEEE 24th Symposium on Computer Arithmetic (ARITH), London, UK, 24-26 July 2017. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781538619650 - 9781538619643 - 9781538619667 ; , s. 62-63
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Konferensbidrag (refereegranskat)abstract
- Approximate matrix inversion based on Neumann series has seen a recent increased interest motivated by massive MIMO systems. There, the matrices are in many cases diagonally dominant, and, hence, a reasonable approximation can be obtained within a few iterations of a Neumann series. In this work, we clarify that the complexity of exact methods are about the same as when three terms are used for the Neumann series, so in this case, the complexity is not lower as often claimed. The second common argument for Neumann series approximation, higher parallelism, is indeed correct. However, in most current practical use cases, such a high degree of parallelism is not required to obtain a low latency realization. Hence, we conclude that a careful evaluation, based on accuracy and latency requirements must be performed and that exact matrix inversion is in fact viable in many more cases than the current literature claims.
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| 3. |
- Ingemarsson, Carl, 1983-, et al.
(författare)
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Finite wordlength properties of matrix inversion algorithms in fixed-point and logarithmic number system
- 2011
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Ingår i: 2011 20th European Conference on Circuit Theory and Design (ECCTD). - Piscataway, NJ, USA : IEEE. - 9781457706189 ; , s. 673-676
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Konferensbidrag (refereegranskat)abstract
- Matrix inversion is sensitive towards the number representation used. In this paper simulations of matrix inversion with numbers represented in the fixed-point and logarithmic number systems (LNS) are presented. A software framework has been implemented to allow extensive simulation of finite wordlength matrix inversion. Six different algorithms have been used and results on matrix condition number, wordlength, and to some extent matrix size are presented. The simulations among other things show that the wordlength requirements differ significantly between different algorithms in both fixed-point and LNS representations. The results can be used as a starting point for a matrix inversion hardware implementation.
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| 4. |
- Ingemarsson, Carl, 1983-, et al.
(författare)
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On fixed-point implementation of symmetric matrix inversion
- 2015
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Ingår i: Proceedings of the European Conference on Circuit Theory and Design (ECCTD). - Piscataway, NJ, USA : IEEE. - 9781479998777 ; , s. 440-443
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Konferensbidrag (refereegranskat)abstract
- In this work we explore the trade-offs between established algorithms for symmetric matrix inversion for fixed-point hardware implementation. Inversion of symmetric positive definite matrices finds applications in many areas, e.g. in MIMO detection and adaptive filtering. We explore computational complexity and show simulation results where numerical properties are analyzed. We show that LDLT decomposition combined with equation system solving are the most promising algorithm for fixed-point hardware implementation. We further show that simply counting the number of operations does not establish a valid comparison between the algorithms as the required word lengths differ significantly.
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| 5. |
- Ingemarsson, Carl, 1983-, et al.
(författare)
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On Using the Logarithmic Number System for Finite Wordlength Matrix Inversion
- 2011
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Ingår i: The 54th IEEE International Midwest Symposium on Circuits and Systems. - Piscataway, NJ, USA : IEEE. - 9781612848570 - 9781612848556 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- Matrix inversion is a key operation in for instance adaptivefilters and MIMO communication system receivers. For ill-conditionedchannel matrices long wordlengths are required for fixed-point implementationof matrix inversion. In this work, the wordlength/error tradeoffsfor matrix inversion using different algorithms with fixed-point andlogarithmic number systems (LNS) are considered. LNS provides higherresolution for small numbers and a larger dynamic range. Also, it willalter the cost of the basic operations in the algorithms. The results showthat also the wordlength required to achieve a comparable error differsignificantly between different algorithms and for most algorithms isreduced for LNS compared to fixed-point.
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| 6. |
- Ingemarsson, Carl, 1983-, et al.
(författare)
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SFF—The Single-Stream FPGA-Optimized Feedforward FFT Hardware Architecture
- 2018
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Ingår i: Journal of Signal Processing Systems. - : Springer. - 1939-8018 .- 1939-8115. ; 90:11, s. 1583-1592
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, a fast Fourier transform (FFT) hardware architecture optimized for field-programmable gate-arrays (FPGAs) is proposed. We refer to this as the single-stream FPGA-optimized feedforward (SFF) architecture. By using a stage that trades adders for shift registers as compared with the single-path delay feedback (SDF) architecture the efficient implementation of short shift registers in Xilinx FPGAs can be exploited. Moreover, this stage can be combined with ordinary or optimized SDF stages such that adders are only traded for shift registers when beneficial. The resulting structures are well-suited for FPGA implementation, especially when efficient implementation of short shift registers is available. This holds for at least contemporary Xilinx FPGAs. The results show that the proposed architectures improve on the current state of the art.
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| 7. |
- Ingemarsson, Carl, 1983-, et al.
(författare)
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Using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAs
- 2012
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Ingår i: 22nd International Conference on Field Programmable Logic and Applications (FPL). - Piscataway, NJ, USA : IEEE Communications Society. - 9781467322560 - 9781467322553 ; , s. 71-74
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Konferensbidrag (refereegranskat)abstract
- Many contemporary FPGAs have introduced a pre-adder before the hard multipliers, primarily aimed at linear-phase FIR filters. In this work, structural modifications are proposed with the aim of reducing the LUT resource utilization and, finally, using the pre-adder for implementing single path delay feedback pipeline FFTs. The results show that two thirds of the LUT resources can be saved when the pre-adder has bypass functionality, as in the Xilinx 6 and 7 series, compared to a direct mapping.
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