| 1. |
- Nurmi, J, et al.
(författare)
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The SoC-mobinet model in system-on-chip education
- 2005
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Ingår i: 2005 IEEE International Conference on Microelectronic Systems Education, Proceedings. - LOS ALAMITOS, CA : IEEE COMPUTER SOC. - 0769523749 ; , s. 71-72
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Konferensbidrag (refereegranskat)abstract
- This paper describes the model of developing SoC curricula jointly by industry and academia, where joint effort research results are turned into course contents for SoC-curricula and industry training activities.
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| 2. |
- Ofner, Erwin, et al.
(författare)
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SoC-Mobinet, R&D and Education in System-on-Chip Design
- 2004
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Ingår i: 2004 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS. - 0780385586 ; , s. 77-80
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Konferensbidrag (refereegranskat)abstract
- With fabrication technologies enabling the integration of a billion transistors and allowing gigahertz frequencies, complex systems (System-on-Chip, SoC) can be realized on a single die. The design of such systems provides tremendous challenges to industry and academia. Universities need to invest a huge effort to restructure their related engineering curricula, which is only possible in close co-operations with industry and other Universities. This paper describes a project, co-funded by the European Commission and by industry, where in a joint effort related research results are turned into course contents for SoC-curricula and industry training activities.
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| 3. |
- Guang, L., et al.
(författare)
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Coarse and fine-grained monitoring and reconfiguration for energy-efficient NoCs
- 2012
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Ingår i: System on Chip (SoC), 2012 International Symposium on. - : IEEE. - 9781467328951 ; , s. 6376351-
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Konferensbidrag (refereegranskat)abstract
- Comparative evaluations of centralized, clustered and distributed architectures, for energy management in NoCs, are presented. The paper starts with the systematic examination of the monitoring, decision-making, and reconfiguration processes in building coarse and fine-grained self-adaptation architectures. With examining the physical support in modern technology, network-wide, cluster-wide and per-node energy-management architectures on NoCs are presented, utilizing either voltage regulators or multiple on-chip power delivery networks (MPNs). To identify the effectiveness and efficiency of energy-performance tradeoffs, extensive quantitative simulations are performed with various temporal and spatially changing traffics. Based on the results, we can first observe that the centralized architecture can not adapt to the traffic's spatial locality for effective energy-performance tradeoff. Second, the distributed energy management has the lowest energy-delay product mostly attributed to the fast voltage switching of MPNs, while the synchronization incurs noticeable energy overhead. The clustered architecture, last but not least, is a suitable alternative when the advanced MPN technology is not available. It has low energy and energy-delay product, with very small energy overhead from the monitoring communication.
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| 4. |
- Guang, L., et al.
(författare)
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HLS-DoNoC : High-level simulator for dynamically organizational NoCs
- 2012
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Ingår i: Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012 IEEE 15th International Symposium on. - : IEEE. - 9781467311854 ; , s. 89-94
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Konferensbidrag (refereegranskat)abstract
- A high-level simulator is presented for the design and analysis of dynamically organizational Networks-on-Chip (DoNoCs). The DoNoC is able to organize statically or dynamically different network nodes for run-time coarse and fine grained reconfiguration, in particular power management. As an important step in the design flow, a simulator for early-stage design exploration is the focus of the paper. Built upon classic wormhole-based NoC architecture, the simulator is capable of experimenting diverse run-time monitoring and reconfiguration methods. In particular, dynamic clusterization can be performed with inter-cluster interfaces properly configured at the run-time. The simulator is flit-level accurate, trace-driven, and easy-to-reconfigure. It supports both synchronous and ratiochronous timing, and can provide the communication performance and power/energy consumption. The paper demonstrates the usage of the simulator in the design of various cluster-based power management schemes.
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| 5. |
- Guang, L., et al.
(författare)
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Survey of self-adaptive NoCs with energy-efficiency and dependability
- 2012
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Ingår i: International Journal of Embedded and Real-Time Communication Systems. - : IGI Global. - 1947-3176 .- 1947-3184. ; 3:2, s. 1-22
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Forskningsöversikt (refereegranskat)abstract
- The self-adaptive Network-on-Chip (NoC) is a promising communication architecture for massively parallel embedded systems. With constant technology scaling and the consequent stronger influence of process variations, the necessity of run-time monitoring and adaptive reconfiguration becomes widely acknowledged. This article presents a survey of existing techniques and methods, in particular for energy efficiency and dependability. The article firstly examines the motivation of self-adaptive computing in parallel embedded systems. A self-adaptive system model is abstracted, which is composed of goals, monitoring interface, and self-adaptation. Based on the model, the authors extensively survey previous works addressing adaptive NoCs with different monitoring techniques and reconfiguration methods, for power/energy optimization and dependability enhancement. Several design examples are elaborated which serve proper guiding purposes. The authors also identify important issues which are often overlooked or deserve more attention. The article provides review and insight for future design on this topic.
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| 6. |
- Isoaho, J A, et al.
(författare)
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New course on computational platforms towards nanoscale systems
- 2005
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Ingår i: 23rd NORCHIP Conference 2005. - : IEEE. - 1424400643 - 9781424400645 ; , s. 226-229
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Konferensbidrag (refereegranskat)abstract
- In this paper we present an educational approach for a paradigm shift needed when changing from deep submicron CMOS designs to real nano andnanoscaletechnologies [7] in complex communication and computationsystemimplementations. Here we present an introductioncourseimplemented for starting the paradigm shift in curriculum. Here we presentcoursetargets, structure and implementation as well as future designer competence profiles. Thecourseis consisting of five thematic areas: nano-scale technologies, parallelplatforms, concurrent algorithms, reconfigurablesystemsand autonomoussystemmanagement. These thematic areas compound the core of future nanosystems educational program upgrades for current NoC curricula.
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| 7. |
- Nigussie, E., et al.
(författare)
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Boosting performance of self-timed delay-insensitive bit parallel on-chip interconnects
- 2011
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Ingår i: IET CIRC DEVICE SYST. - : Institution of Engineering and Technology (IET). - 1751-858X. ; 5:6, s. 505-517
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Tidskriftsartikel (refereegranskat)abstract
- The authors present a performance boosting technique with a better power efficiency for delay-insensitive on-chip interconnects. The increase in signal propagation delay uncertainty with technology scaling makes self-timed delay-insensitive on-chip interconnects the most appropriate alternative. However, achieving high-performance communication in self-timed delay-insensitive links is difficult, especially for large bit parallel transmission because of the time-consuming detection of each bit validity. The authors present a high-speed completion detection technique along with its circuit implementation and two on-chip interconnects which use the proposed completion detection circuit. The performance, power consumption, power efficiency and area of the presented on-chip interconnects are analysed and compared with the conventionally implemented delay-insensitive interconnects. For 64-bit parallel transmission, 2.07 and 1.72 times throughput improvement with 47 and 39% more power efficiency have been achieved for the two interconnects compared to their conventional counterparts. The interconnect circuits are designed and simulated using Cadence Analog Spectre and Hspice with 65 nm complementary metal-oxide semiconductor technology from STMicroelectronics.
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| 8. |
- Nigussie, E., et al.
(författare)
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Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput
- 2012
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1063-8210 .- 1557-9999. ; 20:12, s. 2265-2277
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Tidskriftsartikel (refereegranskat)abstract
- A high-throughput and low-energy semi-serial on-chip communication link based on novel design techniques and circuit solutions is presented. This self-timed link is designed using high-speed serialization/deserializtion and pulse dual-rail encoding techniques. The link also employs wave-pipelined differential pulse current-mode signaling to maintain the high speed data intake from the serializer. The energy efficiency of the proposed semi-serial link, which consists of bit-serial links in parallel, mainly comes from the sharing of the novel serializer's control circuit among the bit-serial links. In addition, the integration of pulse signaling with wave-pipelining, the use of a new low-complexity data validity detection technique, and the avoidance of data decoding logic also contribute to the power reduction. Furthermore, the formulated pulse dual-rail encoding provides an opportunity to implement pulse signaling at no cost. The ability to detect data validity at bit level allows acknowledgment per word without losing the delay-insensitivity of the transmission. The proposed semi-serial link is analyzed and compared with bit-serial and fully bit-parallel links for 64-bit data and communication distances of 1 to 8 mm. The semi-serial link which consists of eight bit-serial links provides 72.72 Gbps throughput with 286 fJ/bit energy dissipation for 8 mm transmission. It dissipates the lowest energy per bit compared to fully bit-parallel links while achieving the same throughput. The links are designed and simulated in Cadence Analog Spectre using 65-nm technology from STMicroelectronics.
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| 9. |
- Gao, Y. H., et al.
(författare)
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A comparison design of comb decimators for sigma-delta analog-to-digital converters
- 2000
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Ingår i: Analog Integrated Circuits and Signal Processing. - 0925-1030 .- 1573-1979. ; 22:1, s. 51-60
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a comparison design of comb decimators based on the non-recursive algorithm and the recursive algorithm. Compared with the recursive algorithm, the main advantage of the non-recursive algorithm is its abilities of reducing power consumption and increasing circuit speed especially when the decimation ratio and filter order are high. Based on the non-recursive algorithm, a decimator with programmable filter orders (3rd, 4th and 5th), decimation ratios (8, 16, 32 and 64) and input bits (1 and 2 bits) has been implemented in a 0.6 mu m 3.3 V CMOS process. Its measured core power consumption is 44 mW at the oversampling rate of 25 MHz and its highest input data rate is 110 MHz.
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| 10. |
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