| 1. |
- Aybek, Mehmet Onur, et al.
(författare)
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From the Synchronous Data Flow Model of Computation to an Automotive Component Model
- 2021
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Ingår i: Proceedings 26th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2021. - : Institute of Electrical and Electronics Engineers (IEEE).
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Konferensbidrag (refereegranskat)abstract
- The size and complexity of automotive software systems are steadily increasing. Software functions are subject to different requirements and belong to different functional domains of the car. Meanwhile, streaming applications have become increasingly relevant in emerging application areas such as Advanced Driving Assistance Systems. Among models for streaming applications, the Synchronous Data Flow model is well-known for its analysable properties. This work presents transformation rules that allow transforming applications described by the Synchronous Data Flow model to an automotive component model. The proposed transformation rules are implemented in form of a software plugin for an automotive tool suite that allows for timing analysis, code synthesis and deployment to a Real-Time Operating System. To demonstrate the applicability of the proposed approach, a case study of a Kalman filter that is part of a simplified cruise control application is presented. An abstract Synchronous Data Flow model of the filter is transformed into a component that is deployed on an Electronic Control Unit with hard timing guarantees.
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| 2. |
- Jordao, Rodolfo, et al.
(författare)
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A multi-view and programming language agnostic framework for model-driven engineering
- 2022
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Ingår i: PROCEEDINGS OF THE 2022 FORUM ON SPECIFICATION & DESIGN LANGUAGES (FDL). - : Institute of Electrical and Electronics Engineers (IEEE).
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Konferensbidrag (refereegranskat)abstract
- Model-driven engineering (MDE) addresses the complexity of modern-day embedded system design. Multiple MDE frameworks are often integrated into a design process to use each MDE framework's state-of-the-art tools for increased productivity. However, this integration requires substantial development effort. In this paper, we propose an MDE, framework based on a formalism of system graphs and trait hierarchies for programming-language-agnostic integration between tools within our framework and with tools of other MDE frameworks. Implementing our framework for each programming language is a one-time development effort. We evaluate our proposal in an MDE design process by developing a Java supporting library and an AMALTHEA connector. Then we perform an MDE, industrial avionics case study with both. The evaluation shows that our framework facilitates the integration of different tools and the independent development of different system parts. Therefore, our framework is a reliable MDE, framework that lowers the effort of integrating tools to benefit from their combined state-of-the-art.
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| 3. |
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| 4. |
- Jordao, Rodolfo, et al.
(författare)
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Design space exploration for safe and optimal mapping of avionics functionality on IMA platforms
- 2023
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Ingår i: AIAA/IEEE Digital Avionics Systems Conference. - : Institute of Electrical and Electronics Engineers (IEEE).
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Konferensbidrag (refereegranskat)abstract
- Future avionic systems will be increasingly automated. The size and complexity of the avionics functions in these systems will increase likewise. The degree of attainable automation directly depends on the avionics system's computing power and the efficiency of available tools that map the overall functionality onto the target heterogeneous platform architecture. In safety-critical scenarios, these automation tools must also provide safety guarantees that aid or drive the certification processes. In line with this automation goal, We propose a novel design space exploration technique for the mapping functionality on IMA platforms. The design space exploration technique returns mappings of the functionality onto the platform that are safe and increasingly resource-efficient. A safe mapping is one where the functional and extra-functional requirements are met. A resource-efficient mapping is one where fewer processing elements are used to achieve a safe mapping. More importantly, the proposed technique can return computational proof that no safe mapping is likely possible. This proof is key for safety-critical contexts. To demonstrate the suitability of our technique for avionics systems design scenarios, we investigate its use with an industrial avionics case based on the ones from the PANORAMA ITEA3 project. The case study includes two avionics functionalities, one control functionality, and one streaming-like functionality. The platform is hierarchical and heterogeneous, with elements oriented for higher safety and elements oriented for higher performance. The avionics case-study evaluation shows that our novel design space exploration technique's abstractions and assumptions adequately represent avionics design scenarios directly or through a systematic overestimation. The technique is openly available within the design space exploration tool IDeSyDe. Therefore, designers can immediately benefit from the optimality and safety guarantees given by our novel design space exploration technique in their avionics design process.
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| 5. |
- Jordao, Rodolfo, et al.
(författare)
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Formulation of Design Space Exploration Problems by Composable Design Space Identification
- 2021
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Ingår i: PROCEEDINGS OF THE 2021 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2021). - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 1204-1207
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Konferensbidrag (refereegranskat)abstract
- Design space exploration (DSE) is a key activity in embedded system design methodologies and can be supported by well-defined models of computation (MoCs) and predictable platform architectures. The original design model, covering the application models, platform models and design constraints needs to be converted into a form analyzable by computer-aided decision procedures such as mathematical programming or genetic algorithms. This conversion is the process of design space identification (DSI), which becomes very challenging if the design domain comprises several MoCs and platforms. For a systematic solution to this problem, separation of concerns between the design domain and decision domain is of key importance. We propose in this paper a systematic DSI scheme that is (a) composable, as it enables the stepwise and simultaneous extension of both design and decision domain, and (b) tuneable, because it also enables different DSE solving techniques given the same design model. We exemplify this DSI scheme by an illustrative example that demonstrates the mechanisms for composition and tuning. Additionally, we show how different compositions can lead to the same decision model as an important property of this DSI scheme.
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| 6. |
- Olthuis, Jorrit J., et al.
(författare)
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VrFy : Verification of Formal Requirements using Generic Traces
- 2021
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Ingår i: 2021 21ST INTERNATIONAL CONFERENCE ON SOFTWARE QUALITY, RELIABILITY AND SECURITY COMPANION (QRS-C 2021). - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 177-183
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Konferensbidrag (refereegranskat)abstract
- In order to fulfil standards governing the development of safety-critical systems, requirements are often shown to be satisfied by means of traditional techniques such as system analysis and testing activities. While these techniques have been used for many years, issues can still arise due to weak tests, not fully covering all requirement scenarios; and due to misinterpretation of requirements, leading to futile test activities. Having simpler techniques to show that requirements are properly fulfilled and that depend less on thoroughness of the tester is beneficial. To tackle these issues, we present an analysis method together with an accompanying toolset, VrFy, implementing a novel technique to automate the detection of violations of requirements. Monitors are generated automatically, and the risk due to misinterpretation of requirements is reduced by using a formal notation (LTL3). Compared to related work, the proposed technique is programming language agnostic and can identify the exact time when requirements are violated, supporting the end user to quickly spot the root cause. By means of a real-world use case in the railway domain, we show how the tool can be used to augment traditional verification techniques.
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| 7. |
- Sander, Ingo, Professor, 1964-, et al.
(författare)
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TOWARDS CORRECT-BY-CONSTRUCTION DESIGN OF SAFETY-CRITICAL EMBEDDED AVIONICS SYSTEMS
- 2022
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Ingår i: 33rd Congress of the International Council of the Aeronautical Sciences, ICAS 2022. - : International Council of the Aeronautical Sciences. ; , s. 1637-1658
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Konferensbidrag (refereegranskat)abstract
- New methodologies are needed for the development of avionics systems to meet today’s software explosion in complexity and related cost due to the increased functionality in the aircraft. Current design flows for software-intensive systems do not have a clear path from the functional specification to the final implementation and cannot provide real-time guarantees. The situation will become even more difficult because, in the future, more and more applications will share the same computation nodes and the network in a distributed hierarchical network-based system. In order to overcome the present situation, a novel methodology for a correct-by-construction design of safety-critical embedded avionics systems has been created and formulated within the Vinnova NFFP7 project CORRECT. Correct-by-construction design is a radical departure from current design practice, with the potential to decrease the verification costs for future systems significantly. The paper presents the underlying foundation of the methodology, its carefully selected ingredients, and discuss available results and existing tool support. The methodology is based on a disciplined system modelling environment grounded on a sound formal foundation, a design space exploration technique, and a clear path to hardware and software synthesis. An industrial case study investigates the potential of the methodology.
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| 8. |
- Schwartz, Christofer, et al.
(författare)
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On-board Satellite Data Processing to Achieve Smart Information Collection
- 2022
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Ingår i: Proceedings of SPIE - The International Society for Optical Engineering. - : SPIE-Intl Soc Optical Eng. - 9781510651524
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Konferensbidrag (refereegranskat)abstract
- Nowadays, it is a reality to launch, operate, and utilize small satellites at an affordable cost. However, bandwidth constraint is still an important challenge. For instance, multispectral and hyperspectral sensors generate a significant amount of data subjected to communication channel impairments, which is addressed mainly by source and channel coding aiming at an effective transmission. This paper targets a significant further bandwidth reduction by proposing an on-the-fly analysis technique on the satellite to decide which information is effectively useful for specific target applications, before coding and transmitting. The challenge would be detecting clouds and vessels having the measurements of red-band, green-band, blue-band, and near infrared band, aiming at sufficient probability of detection, avoiding false alarms. Furthermore, the embedded platform constraints must be satisfied. Experiments for typical scenarios of summer and winter days in Stockholm, Sweden, are conducted using data from the Mimir’s Well, the Saab AI-based data fusion system. Results show that non-relevant content can be identified and discarded, pointing out that for the cloudy scenarios evaluated, up to 73.1% percent of image content can be suppressed without compromising the useful information into the image. For the water regions in the scenarios containing vessels, results indicate that a stringent amount of data can be discarded (up to 98.5%) when transmitting only the regions of interest (ROI).
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| 9. |
- Ungureanu, George, et al.
(författare)
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Exploiting Dataflow Models for Parallel Simulation of Discrete Timed Systems
- 2020
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Ingår i: Proceedings of the 2020 Forum for Specification & Design Languages (FDL). - Kiel, Germany : Institute of Electrical and Electronics Engineers (IEEE).
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Konferensbidrag (refereegranskat)abstract
- The shift towards parallel computing witnessed since the turn of this century has forced us to rethink traditional software design paradigms to better utilize resources. Yet, the simulation of time-aware systems remains a challenging topic due to the inherent semantics of time and causality whose consistency needs to be controlled, traditionally in form of a global event queue, limiting the potential for parallel exploitation. We propose a rehash of this problem by tackling it from a different modeling perspective, one which is able to express concurrency more naturally, i.e. dataflow (DF) models of computation (MoCs). By abstracting time aspects as an algebra hosted on a pure DF MoC, we are able to apply recent results from MoC theory not only for the purpose of describing deterministic behaviors for distributed timed systems, but also to overcome the existing limitations of timed execution in order to increase a simulation model's performance. We use a well-known example of a deadlock-prone distributed discrete event system as a driver to introduce the modeling concepts and show their potential for parallelism.
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| 10. |
- Yang, Yu, et al.
(författare)
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Optimizing BCPNN Learning Rule for Memory Access
- 2020
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Ingår i: Frontiers in Neuroscience. - : Frontiers Media SA. - 1662-4548 .- 1662-453X. ; 14
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Tidskriftsartikel (refereegranskat)abstract
- Simulation of large scale biologically plausible spiking neural networks, e.g., Bayesian Confidence Propagation Neural Network (BCPNN), usually requires high-performance supercomputers with dedicated accelerators, such as GPUs, FPGAs, or even Application-Specific Integrated Circuits (ASICs). Almost all of these computers are based on the von Neumann architecture that separates storage and computation. In all these solutions, memory access is the dominant cost even for highly customized computation and memory architecture, such as ASICs. In this paper, we propose an optimization technique that can make the BCPNN simulation memory access friendly by avoiding a dual-access pattern. The BCPNN synaptic traces and weights are organized as matrices accessed both row-wise and column-wise. Accessing data stored in DRAM with a dual-access pattern is extremely expensive. A post-synaptic history buffer and an approximation function thus are introduced to eliminate the troublesome column update. The error analysis combining theoretical analysis and experiments suggests that the probability of introducing intolerable errors by such optimization can be bounded to a very small number, which makes it almost negligible. Derivation and validation of such a bound is the core contribution of this paper. Experiments on a GPU platform shows that compared to the previously reported baseline simulation strategy, the proposed optimization technique reduces the storage requirement by 33%, the global memory access demand by more than 27% and DRAM access rate by more than 5%; the latency of updating synaptic traces decreases by roughly 50%. Compared with the other similar optimization technique reported in the literature, our method clearly shows considerably better results. Although the BCPNN is used as the targeted neural network model, the proposed optimization method can be applied to other artificial neural network models based on a Hebbian learning rule.
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