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- Abdul Waheed, Malik, 1981-, et al.
(författare)
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Generalized Architecture for a Real-time Computation of an Image Component Features on a FPGA
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Annan publikation (övrigt vetenskapligt/konstnärligt)abstract
- This paper describes a generalized architecture for real-time component labeling and computation of image component features. Computing real-time image component features is one of the most important paradigms for modern machine vision systems. Embedded machine vision systems demand robust performance, power efficiency as well as minimum area utilization. The presented architecture can easily be extended with additional modules for parallel computation of arbitrary image component features. Hardware modules for component labeling and feature calculation run in parallel. This modularization makes the architecture suitable for design automation. Our architecture is capable of processing 390 video frames per second of size 640x480 pixels. Dynamic power consumption is 24.20mW at 86 frames per second on a Xilinx Spartran6 FPGA.
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| 2. |
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| 3. |
- Havashki, Asghar, et al.
(författare)
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Analysis of switching activity in DSP signals in the presence of noise
- 2009
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Ingår i: IEEE EUROCON. - Piscataway : IEEE. ; , s. 234-239
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Konferensbidrag (refereegranskat)abstract
- Input switching activity is one of the deciding factors for power consumption in digital signal processing components. For accurate power estimation, it is essential to have knowledge about the switching activity in the input signal, including how this activity changes in different environments, e.g., in the presence of noise. The dual bit type (DBT) method aims at characterizing the bit-level switching activity in a signal, using signal statistics. However, the DBT method requires that the correlation coefficient and switching activity for the most significant bit of the signal are available. In this paper we give an expression for direct calculation of the correlation coefficient for the most significant bit in a signal, using the word-level correlation coefficient. Using simulation results we examine the accuracy of the given method to calculate the switching activity and correlation coefficient for the most significant bit. Furthermore, we derive expressions for accurately calculating the variance and word-level correlation coefficient for a correlated signal, when an additional noise of a given variance is added to the signal. This can be used to estimate the bit-level switching activity in a signal in the presence of noise. Finally, based on this we study the impact the additional noise has on the switching activity of the resulting signal.
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| 4. |
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| 5. |
- Tahmasbi Oskuii, Saeeid, et al.
(författare)
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Power optimized partial product reduction interconnect ordering in parallel multipliers
- 2007
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Ingår i: Norchip,2007. - Piscataway : IEEE.
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Konferensbidrag (refereegranskat)abstract
- When designing the reduction tree of a parallel multiplier, we can exploit a large intrinsic freedom for the interconnection order of partial products. The transition activities vary significantly for different internal partial products. In this work we propose a method for generation of power-efficient parallel multipliers in such a way that its partial products are connected to minimize activity. The reduction tree is designed progressively. A Simulated Annealing optimizer uses power cost numbers from a specially implemented probabilistic gate-level power estimator and selects a power-efficient solution for each stage of the reduction tree. VHDL simulation using ModelSim shows a significant reduction in the overall number of transitions. This reduction ranges from 15% up to 32% compared to randomly generated reduction trees and is achieved without any noticeable area or performance overhead.
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| 7. |
- Thörnberg, Benny, et al.
(författare)
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Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems
- 2007
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Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - 0278-0070 .- 1937-4151. ; 26:4, s. 781-800
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Tidskriftsartikel (refereegranskat)abstract
- The great variety of pixel dynamics of real-time video processing systems, ranging from color, grayscale or binary pixels, means that a careful design and specification of bit-widths is required. It is obvious that the bit-width specification will affect the total memory storage requirement. However, what is not so obvious is that the bit-width specification will also affect the design of the memory hierarchy, an impact similar for both hardware and software implementations. We have developed an Integer Non Linear Program (INLP) formulation for the optimization of the memory hierarchy of real-time video processing systems. An active surveillance video camera is introduced as a test case. We demonstrate how the optimization model can reduce the on-chip memory storage by 61 percent compared to a non optimal memory hierarchy.
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| 8. |
- Thörnberg, Benny, et al.
(författare)
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Polyhedral space generation and memory estimation from interface and memory models of real-time video systems
- 2006
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Ingår i: Journal of Systems and Software. - : Elsevier BV. - 0164-1212 .- 1873-1228. ; 79:2, s. 231-245
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Tidskriftsartikel (refereegranskat)abstract
- We present a tool and a methodology for estimating the memory storage requirement for synchronous real-time video processing systems. Typically, a designer will use the feedback information from this estimation to select the most optimal execution order for software processors or space to time mapping for hardware. We propose to start from a conceptual interface and memory model that captures memory usage and data transfers. This high-level modeling is provided as an extension library of SystemC called IMEM. A common polyhedral iteration space is generated from the model, where polytopes are placed using a new placement algorithm based on simple heuristics. This algorithm will ensure maximum freedom of selecting executing order as all negative dependencies are removed to the length of zero. A demonstration is given regarding how the polytopes and dependency vectors can then be used as input to a memory storage estimation tool called STOREQ.
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