| 1. |
- Abbasi, Morteza, 1982, et al.
(författare)
-
A Broadband 60-to-120 GHz single-chip MMIC multiplier chain
- 2009
-
Ingår i: IEEE MTT-S International Microwave Symposium Digest. - 0149-645X. ; , s. 441-444
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a single-chip 60 GHz to 120 GHz frequency multiplier chain based on 0.1 ?m GaAs mHEMT. The MMIC can deliver 3 to 5 dBm of output power from 110 GHz to 130 GHz with 2 dBm input power and consumes only 65 mW of DC power. The signal at the fundamental frequency is suppressed more than 20 dB over the band of interest. The impedance matching networks are realized using coupled transmission lines.
|
|
| 2. |
- Abbasi, Morteza, 1982, et al.
(författare)
-
Single-Chip 220-GHz Active Heterodyne Receiver and Transmitter MMICs With On-Chip Integrated Antenna
- 2011
-
Ingår i: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480 .- 1557-9670. ; 59:2, s. 466-478
-
Tidskriftsartikel (refereegranskat)abstract
- This paper presents the design and characterization of single-chip 220-GHz heterodyne receiver (RX) and transmitter (TX) monolithic microwave integrated circuits (MMICs) with integrated antennas fabricated in 0.1-mu m GaAs metamorphic high electron-mobility transistor technology. The MMIC receiver consists of a modified square-slot antenna, a three-stage low-noise amplifier, and a sub-harmonically pumped resistive mixer with on-chip local oscillator frequency multiplication chain. The transmitter chip is the dual of the receiver chip by inverting the direction of the RF amplifier. The chips are mounted on 5-mm silicon lenses in order to interface the antenna to the free space and are packaged into two separate modules. The double-sideband noise figure (NF) and conversion gain of the receiver module are measured with the Y-factor method. The total noise temperature of 1310 +/- 100K(corresponding to an NF of 7.4 dB), including the losses in the lens and antenna, is measured at 220 GHz with a respective conversion gain of 3.5 dB. The radiated continuous-wave power from the transmitter module is measured to be up to -6 dBm from 212 to 226 GHz. The transmitter and receiver are linked in a quasi-optical setup and the IF to IF response is measured to be flat up to 10 GHz. This is verified to be usable for transmission of a 12.5-Gb/s data stream between the transmit and receive modules over a 0.5-m wireless link. The modules operate with a 1.3-V supply and each consume 110-mW dc power. The presented 220-GHz integrated circuits and modules can be used in a variety of applications, including passive and active imaging, as well as high-speed data communications. To the best of our knowledge, these MMICs are the highest frequency single-chip low-noise heterodyne receiver and transmitter pair reported to date.
|
|
| 3. |
- Abbasi, Morteza, 1982, et al.
(författare)
-
Single-Chip Frequency Multiplier Chains for Millimeter-Wave Signal Generation
- 2009
-
Ingår i: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480 .- 1557-9670. ; 57:12, s. 3134-3142
-
Tidskriftsartikel (refereegranskat)abstract
- Two single-chip frequency multiplier chains targeting 118 and 183 GHz output frequencies are presented. The chips are fabricated in a 0.1 mu m GaAs metamorphic high electron-mobility transistor process. The D-band frequency doubler chain covers 110 to 130 GHz with peak output power of 5 dBm. The chip requires 2 dBm input power and consumes only 65 mW of dc power. The signal at the fundamental frequency is suppressed more than 25 dB compared to the desired output signal over the band of interest. The G-band frequency sextupler (x6) chain covers 155 to 195 GHz with 0 dBm peak output power and requires 6.5 dBm input power and 92.5 mW dc power. The input signal to the multiplier chain can be reduced to 4 dBm while the output power drops only by 0.5 dB. The unwanted harmonics are suppressed more than 30 dB compared to the desired signal. An additional 183 GHz power amplifier is presented to be used after the x6 frequency multiplier chain if higher output power is required. The amplifier delivers 5 dBm output power with a small-signal gain of 9 dB from 155 to 195 GHz. The impedance matching networks are realized using coupled transmission lines which is shown to be a scalable and straightforward structure to use in amplifier design. Microstrip transmission lines are used in all the designs.
|
|
| 4. |
- Bao, M., et al.
(författare)
-
14 Gbps on-off keying modulator and demodulator for D-band communication
- 2014
-
Ingår i: 2014 IEEE International Wireless Symposium (IWS), 24-26 March 2014, X'ian. - 9781479934034 ; , s. (4 pp)-
-
Konferensbidrag (refereegranskat)abstract
- An on-off keying (OOK) modulator and demodulator operating at carrier frequency from 100 GHz to 150 GHz are designed and manufactured in a 0.25 μm InP DHBT Technology. The modulator is based on a switch controlled frequency quadrupler, which is driven by input data and a sinusoid signal source. A power detector consisting of a 4-way power divider and four identical active power detector units is proposed as an OOK demodulator. Combining the output of the detector units enables reducing of the ripple at the output by suppressing the 1st, the 2nd, and the 3rd harmonics due to the phase cancellation. The modulator and demodulator are characterized by on-wafer measurements. As an integrated OOK modulator and demodulator, high data rate transmission up to 14 Gbps is demonstrated. At data rate of 13 Gbps, BER
|
|
| 5. |
- Bao, Mingquang, 1962, et al.
(författare)
-
A High-Speed Power Detector for D-Band Communication
- 2014
-
Ingår i: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480 .- 1557-9670. ; 62:7, s. 1515-1524
-
Tidskriftsartikel (refereegranskat)abstract
- A D-band power detector (PD) consisting of a four-way power divider and four identical active PD units is proposed, where four individual PD units are derived by the input signals having the same amplitude, but a 90 degrees phase difference. The outputs of the PD units are combined, to suppress the first, second, and third harmonics due to phase cancellation. Consequently, the ripple at the output is minimized. The proposed PD is designed and manufactured in a 0.25-mu m InP DHBT technology, which is characterized by on-chip measurements with both a sinusoidal signal and a binary amplitude shift-keying modulated signal at a data rate up to 13 Gb/s over different carrier frequencies from 100 to 150 GHz. Measured bit error rate for a 2(7) - 1 pseudorandom binary sequence is less than 10(-12) at the carrier frequency of 120 GHz, and less than 1.7 x 10(-5) at the carrier frequency of 150 GHz. In addition, the proposed PD achieves state-of-the-art power/energy efficiency, which exhibits the lowest energy per bit of 1.1 pJ/bit. Total dc power consumption of the PD is 15 mW.
|
|
| 6. |
- Bao, Mingquang, 1962, et al.
(författare)
-
A novel frequency multiplier
- 2013
-
Patent (övrigt vetenskapligt/konstnärligt)abstract
- It is an object to obtain a frequency multiplier which simultaneously can generate more than one multiple of an input frequency. This object is obtained by means of a frequency multiplier which comprises a first and a second stage connected in series with each other. The first stage is arranged to receive an input AC signal and to generate an output signal comprising harmonics of the input AC signal and to deliver these harmonics to the second stage, which is arranged to receive the output signal from the first stage.In the frequency multiplier, the second stage comprises integer N bipolar/FET transistors, each of which is arranged to receive the output signal from the first stage at its base/gate and to be biased by means of a base/gate bias voltage. In the frequency multiplier’s second stage, the base/gate bias voltage of transistor number n in the second stage is higher than that of transistor number n+1, and each of the N transistors in the second stage has its collector/drain connected to a high pass filter.
|
|
| 7. |
- Bao, M. Q., et al.
(författare)
-
A D-Band Frequency Sixtupler MMIC With Very Low DC Power Consumption
- 2016
-
Ingår i: IEEE Microwave and Wireless Components Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 1558-1764 .- 1531-1309. ; 26:9, s. 726-728
-
Tidskriftsartikel (refereegranskat)abstract
- A novel frequency sixtupler is proposed and verified experimentally. It consists of an even-order harmonics generating stage and a mixing stage to convert the 2nd and the 4th harmonics into the 6th harmonic. Transistors in those two stages operate in class-C condition, thus, the sixtupler consumes very low DC power. A proof-of-concept circuit is designed and manufactured in a 0.25 mu m InP DHBT Technology. The sixtupler delivers a maximum output power of -3.5 dBm at 121 GHz at an input power of 7 dBm. Its 3-dB bandwidth of the output power is 25 GHz in the frequency range from 100 GHz to 125 GHz. It demonstrates also more than 10 dBc rejection ratio of the unwanted harmonics in the frequency range from 110 to 125 GHz. The sixtupler consumes a DC power of only 20 mW, which to the authors knowledge, is the lowest among sixtuplers published so far. The sixtupler also achieves a state-of-the-art peak power efficiency of 1.9%.
|
|
| 8. |
- Bao, M. Q., et al.
(författare)
-
A D-Band Keyable High Efficiency Frequency Quadrupler
- 2014
-
Ingår i: IEEE Microwave and Wireless Components Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 1558-1764 .- 1531-1309. ; 24:11, s. 793-795
-
Tidskriftsartikel (refereegranskat)abstract
- A D-band frequency quadrupler consisting of two cascaded push-push doublers is designed and manufactured in a 0.25 mu m InP DHBT technology. Each doubler has a Marchand balun implemented by broadside-coupled transmission lines, folded in a rectangular shape. The second balun, operating at a half of output frequency, is located inside of the first one for minimizing the chip size. The frequency quadrupler with a dc power consumption of 47 mW has a maximum conversion gain of 2 dB, and exhibits 12 to 25 dBc rejection ratio of the undesired first to fifth harmonics in the frequency range from 110 to 130 GHz. The quadrupler demonstrates a power efficiency of 10%, which is the highest among published quadruplers, as well as the highest conversion gain and an output power of 5 similar to 7 dBm without using power amplifiers. The chip size is 0.77 mm(2). By switching a cascode transistor, the quadrupler can also be used as an on-off keying modulator.
|
|
| 9. |
- Bao, M. Q., et al.
(författare)
-
A High Power-Efficiency D-Band Frequency Tripler MMIC With Gain Up to 7 dB
- 2014
-
Ingår i: IEEE Microwave and Wireless Components Letters. - 1558-1764 .- 1531-1309. ; 24:2, s. 123-125
-
Tidskriftsartikel (refereegranskat)abstract
- A novel frequency tripler consisting of a harmonics generating stage and a converting stage is proposed. A common-emitter transistor in the first stage is used to produce mainly the first to third harmonics, while, a common-emitter transistor in the second stage converts simultaneously the first and the second harmonics into the third harmonic, and also amplifies the third harmonic at the input. The third harmonics obtained from different mechanisms add in favorably phase, and consequently improving the tripler's conversion gain. A proof-of-concept circuit is designed and manufactured in a 0.25 mu m InP DHBT Technology. The tripler has a conversion gain between 0 dB to 7 dB in the output frequency range from 110 to 155 GHz. It demonstrates also up to 30 dBc rejection ratio of the undesired first, the second and the fourth harmonics. The tripler consumes a dc power of only 45 mW, and achieves a state-of-the-art peak power efficiency of 20.2%, which to the authors' knowledge, is the highest obtained among triplers with positive gain published so far.
|
|
| 10. |
|
|
