| 1. |
- Bardizbanyan, Alen, 1986, et al.
(författare)
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Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB)
- 2013
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Ingår i: Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2013. - 9781467355254 ; , s. 269-279
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Konferensbidrag (refereegranskat)abstract
- The need for energy efficiency continues to grow for many classes of processors, including those for which performance remains vital. Data cache is crucial for good performance, but it also represents a significant portion of the processor's energy expenditure. We describe the implementation and use of a tagless access buffer (TAB) that greatly improves data access energy efficiency while slightly improving performance. The compiler recognizes memory reference patterns within loops and allocates these references to a TAB. This combined hardware/software approach reduces energy usage by (1) replacing many level-one data cache (L1D) accesses with accesses to the smaller, more power-efficient TAB; (2) removing the need to perform tag checks or data translation lookaside buffer (DTLB) lookups for TAB accesses; and (3) reducing DTLB lookups when transferring data between the L1D and the TAB. Accesses to the TAB occur earlier in the pipeline, and data lines are prefetched from lower memory levels, which result in asmall performance improvement. In addition, we can avoid many unnecessary block transfers between other memory hierarchy levels by characterizing how data in the TAB are used. With a combined size equal to that of a conventional 32-entry register file, a four-entry TAB eliminates 40% of L1D accesses and 42% of DTLB accesses, on average. This configuration reduces data-access related energy by 35% while simultaneously decreasing execution time by 3%.
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| 2. |
- Björk, Magnus, 1977, et al.
(författare)
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Exposed Datapath for Efficient Computing
- 2006
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Rapport (övrigt vetenskapligt/konstnärligt)abstract
- We introduce FlexCore, which is the first exemplar of a processor based on the FlexSoC processor paradigm. TheFlexCore utilizes an exposed datapath for increased performance. Microbenchmarks yield a performance boost of a factor of two over a traditional five-stage pipeline with the same functional units as the FlexCore.We describe our approach to compiling for the FlexCore.A flexible interconnect allows the FlexCore datapath to bedynamically reconfigured as a consequence of code generation. Additionally, specialized functional units may be introduced and utilized within the same architecture and compilation framework. The exposed datapath requires a wide control word. The conducted evaluation of two micro benchmarks confirms that this increases the instruction bandwidth and memory footprint. This calls for an efficient instruction decoding as proposed in the FlexSoC paradigm.
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| 3. |
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| 4. |
- Hughes, John, 1958, et al.
(författare)
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FlexSoC: Combining Flexibility and Efficiency in SoC Designs
- 2003
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Ingår i: Proceedings of 21st Norchip Conference. ; Riga, Latvia, s. 52-55
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Konferensbidrag (refereegranskat)abstract
- The FlexSoC project aims at developing a designframework that makes it possible to combine the computational speed and energy-efficiency of specialized hardware accelerators with the flexibility of programmable processors. FlexSoC approaches this problem by defining auniform programming interface across the heterogeneousstructure of processing resources. This paper justifies ourapproach and also discusses the central research issueswe will focus on in the areas of VLSI design, computerarchitecture, and programming and verification.
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| 5. |
- Szczerba, Krzysztof, 1985, et al.
(författare)
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Impact of Forward Error Correction on Energy Consumption of VCSEL-based Transmitters
- 2015
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Ingår i: 41st European Conference on Optical Communication, ECOC 2015, Valencia, Spain, 27 September - 1 October 2015. - 9788460817413 ; 2015-November
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Konferensbidrag (refereegranskat)abstract
- We present an analysis of the effect of FEC on energy consumption of VCSEL based transmitters for short-range optical links. We show that a low-complexity FEC can reduce the overall energy consumption of the transmitter.
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| 6. |
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| 7. |
- Thuresson, Martin, 1977, et al.
(författare)
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FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
- 2009
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Ingår i: Journal of Signal Processing Systems. - : Springer Science and Business Media LLC. - 1939-8115 .- 1939-8018. ; 57:1, s. 5-19
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Tidskriftsartikel (refereegranskat)abstract
- We introduce FlexCore, the first exemplar of an architecture based on the FlexSoC framework. Comprising the same datapath units found in a conventional five-stage pipeline, the FlexCore has an exposed datapath control and a flexible interconnect to allow the datapath to be dynamically reconfigured as a consequence of code generation. Additionally, the FlexCore allows specialized datapath units to be inserted and utilized within the same architecture and compilation framework.This study shows that, in comparison to a conventional five-stage general-purpose processor, the FlexCore is up to 40\% more efficient in terms of cycle count on a set of benchmarks from the embedded application domain. We show that both the fine-grained control and the flexible interconnect contribute to the speedup. Furthermore, our synthesized, placed and routed FlexCore offers savings both in energy and execution time.The exposed FlexCore datapath requires a wide control word. The conducted evaluation confirms that this increases the instruction bandwidth and memory footprint. This calls for efficient instruction decoding as proposed in the FlexSoC framework.
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| 8. |
- Ahmad, Tauseef, 1986, et al.
(författare)
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Methodology for Power-Aware Coherent Receiver Design
- 2013
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Ingår i: Optics InfoBase Conference Papers. - 2162-2701. ; , s. SPT4D.4-
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Konferensbidrag (refereegranskat)abstract
- We describe a methodology to design and evaluate DSP hardware for a coherent receiver. Important parameters that can be assessed include DSP power consumption and chip area.
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| 9. |
- Alvandporu, Atila, 1960-, et al.
(författare)
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Impact of Miller Capacitance on Power Consumption
- 1998
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Ingår i: In proceedings of: International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS. ; , s. 83-92
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Konferensbidrag (refereegranskat)
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| 10. |
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