| 1. |
- Lawal, Najeem, 1974-
(författare)
-
Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
- 2009
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include machine vision, object recognition and tracking, visual enhancement and surveillance. Developments in field programmable gate arrays (FPGAs) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operations are currently available and are optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis. A method for the optimised use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) modules for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimised use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components. The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components.
|
|
| 3. |
- Imran, Muhammad
(författare)
-
Investigation of Architectures for Wireless Visual Sensor Nodes
- 2011
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Wireless visual sensor network is an emerging field which has proveduseful in many applications, including industrial control and monitoring,surveillance, environmental monitoring, personal care and the virtual world.Traditional imaging systems used a wired link, centralized network, highprocessing capabilities, unlimited storage and power source. In manyapplications, the wired solution results in high installation and maintenancecosts. However, a wireless solution is the preferred choice as it offers lessmaintenance, infrastructure costs and greater scalability.The technological developments in image sensors, wirelesscommunication and processing platforms have paved the way for smartcamera networks usually referred to as Wireless Visual Sensor Networks(WVSNs). WVSNs consist of a number of Visual Sensor Nodes (VSNs)deployed over a large geographical area. The smart cameras can performcomplex vision tasks using limited resources such as batteries or alternativeenergy sources, embedded platforms, a wireless link and a small memory.Current research in WVSNs is focused on reducing the energyconsumption of the node so as to maximise the life of the VSN. To meet thischallenge, different software and hardware solutions are presented in theliterature for the implementation of VSNs.The focus in this thesis is on the exploration of energy efficientreconfigurable architectures for VSNs by partitioning vision tasks on software,hardware platforms and locality. For any application, some of the vision taskscan be performed on the sensor node after which data is sent over the wirelesslink to the server where the remaining vision tasks are performed. Similarly,at the VSN, vision tasks can be partitioned on software and the hardwareplatforms.In the thesis, all possible strategies are explored, by partitioning visiontasks on the sensor node and on the server. The energy consumption of thesensor node is evaluated for different strategies on software platform. It isobserved that performing some of the vision tasks on the sensor node andsending compressed images to the server where the remaining vision tasks areperformed, will have lower energy consumption.In order to achieve better performance and low power consumption,Field Programmable Gate Arrays (FPGAs) are introduced for theimplementation of the sensor node. The strategies with reasonable designtimes and costs are implemented on hardware-software platform. Based onthe implementation of the VSN on the FPGA together with micro-controller,the lifetime of the VSN is predicted using the measured energy values of theplatforms for different processing strategies. The implementation resultsprove our analysis that a VSN with such characteristics will result in a longerlife time.
|
|
