| 1. |
- Gottlob, H. D. B., et al.
(författare)
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Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics
- 2009
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 86:7-9, s. 1642-1645
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Tidskriftsartikel (refereegranskat)abstract
- We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high-k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd2O3) from a silicon oxide (SiO2) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). (C) 2009 Elsevier B.V. All rights reserved.
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| 2. |
- Abermann, S., et al.
(författare)
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Processing and evaluation of metal gate/high-k/Si capacitors incorporating Al, Ni, TiN, and Mo as metal gate, and ZrO2 and HfO2 as high-k dielectric
- 2007
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84:5-8, s. 1635-1638
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Tidskriftsartikel (refereegranskat)abstract
- We evaluate various metal gate/high-k/Si capacitors by their resulting electrical characteristics. Therefore, we process MOS gate stacks incorporating aluminium (Al), nickel (Ni), titanium-nitride (TiN), and molybdenum (Mo) as the gate material, and metal organic chemical vapour deposited (MOCVD) ZrO2 and HfO2 as the gate dielectric, respectively. The influence of the processing sequence - especially of the thermal annealing treatment - on the electrical characteristics of the various gate stacks is being investigated. Whereas post metallization annealing in forming gas atmosphere improves capacitance-voltage behaviour (due to reduced interface-, and oxide charge density), current-voltage characteristics degrade due to a higher leakage current after thermal treatment at higher temperatures. The Flatband-voltage values for the TiN-, Mo-, and Ni-capacitors indicate mid-gap pinning of the metal gates, however, Ni seems to be thermally unstable on ZrO2, at least within the process scheme we applied.
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| 3. |
- Engström, Olof, 1943, et al.
(författare)
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A generalised methodology for oxide leakage current metric
- 2008
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Ingår i: Proceeding of 9th European Workshop on Ultimate Integration of Silicon (ULIS), Udine, Italy. - 9781424417308 ; , s. 167-
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Konferensbidrag (refereegranskat)abstract
- From calculations of semiconductor interfacecharge, oxide voltage and tunneling currents for MOSsystems with equivalent oxide thickness (EOT) in therange of 1 nm, rules are suggested for making itpossible to compare leakage quality of different oxideswith an accuracy of a factor 2 – 3 if the EOT is known.The standard procedure suggested gives considerablybetter accuracy than the commonly used method todetermine leakage at VFB+1V for n-type and VFB-1V forp-type substrates.
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| 4. |
- Engström, Olof, 1943, et al.
(författare)
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Gate stacks
- 2013
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Ingår i: Nanoscale CMOS: Innovative Materials, Modeling and Characterization. - : Wiley. ; , s. 23 - 67
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Bokkapitel (övrigt vetenskapligt/konstnärligt)
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| 5. |
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| 6. |
- Engström, Olof, 1943, et al.
(författare)
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Properties of Metal/High-k Oxide/Graphene Structures
- 2017
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Ingår i: ECS Transactions. - : The Electrochemical Society. - 1938-5862 .- 1938-6737. ; 80:1, s. 157-176
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Konferensbidrag (refereegranskat)abstract
- The challenge of interpreting experimental data from capacitance versus voltage (C-V) measurements on metal/high-k oxide/graphene (MOG) structures is discussed. Theoretical expressions for the influence of interface states, bulk oxide traps, measurement frequency, temperature and puddles are derived and compared with experiments. The nature of oxide traps and their impact on C-V data is treated especially from the view of electron-lattice interaction at electron emission and capture and possible performance as border traps, resembling interface states. We find that characterization on detailed physical origins leading to effects on C-V data is a more complicated issue than the corresponding analysis of metal/oxide/semiconductor (MOS) structures.
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| 7. |
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| 8. |
- Hurley, P.K., et al.
(författare)
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Interface Defects in HfO2, LaSiOx, and Gd2O3 High-k/MetalGate Structures on Silicon
- 2008
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Ingår i: J. Electrochem. Soc.. ; 155:2, s. G13-G20
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Tidskriftsartikel (refereegranskat)abstract
- In this work, we present experimental results examining the energy distribution of the relatively high (>1×10^11 cm−2) electrically active interface defects which are commonly observed in high-dielectric-constant (high-k) metal–insulator–silicon systems during high-k process development. This paper extends previous studies on the Si(100)/SiOx/HfO2 system to include a comparative analysis of the density and energy distribution of interface defects for HfO2, lanthanum silicate (LaSiOx), and Gd2O3 thin films on (100) orientation silicon formed by a range of deposition techniques. The analysis of the interface defect density across the energy gap, for samples which experience no H2/N2 annealing following the gate stack formation, reveals a peak density (~2×10^12 cm−2 eV−1 to ~1×10^13 cm−2 eV−1) at 0.83–0.92 eV above the silicon valence bandedge for the HfO2, LaSiOx, and Gd2O3 thin films on Si(100). The characteristic peak in the interface state density (0.83–0.92 eV) is obtained for samples where no interface silicon oxide layer is observed from transmission electron microscopy. Analysis suggests silicon dangling bond (Pbo) centers as the common origin for the dominant interface defects for the various Si(100)/SiOx/high-k/metal gate systems. The results of forming gas (H2/N2) annealing over the temperature range 350–555°C are presented and indicate interface state density reduction, as expected for silicon dangling bond centers. The technological relevance of the results is discussed.
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| 9. |
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| 10. |
- Illarionov, Yu Yu, et al.
(författare)
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Bias-temperature instability in single-layer graphene field-effect transistors
- 2014
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Ingår i: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 105:14, s. 143507-
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Tidskriftsartikel (refereegranskat)abstract
- We present a detailed analysis of the bias-temperature instability (BTI) of single-layer graphene field-effect transistors. Both negative BTI and positive BTI can be benchmarked using models developed for Si technologies. In particular, recovery follows the universal relaxation trend and can be described using the established capture/emission time map approach. We thereby propose a general methodology for assessing the reliability of graphene/dielectric interfaces, which are essential building blocks of graphene devices. (C) 2014 AIP Publishing LLC.
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