| 1. |
- Bell, D. C., et al.
(författare)
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Precision cutting and patterning of graphene with helium ions
- 2009
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Ingår i: Nanotechnology. - : IOP Publishing. - 0957-4484 .- 1361-6528. ; 20:45, s. 455301-
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Tidskriftsartikel (refereegranskat)abstract
- We report nanoscale patterning of graphene using a helium ion microscope configured for lithography. Helium ion lithography is a direct-write lithography process, comparable to conventional focused ion beam patterning, with no resist or other material contacting the sample surface. In the present application, graphene samples on Si/SiO(2) substrates are cut using helium ions, with computer controlled alignment, patterning, and exposure. Once suitable beam doses are determined, sharp edge profiles and clean etching are obtained, with little evident damage or doping to the sample. This technique provides fast lithography compatible with graphene, with similar to 15 nm feature sizes.
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| 2. |
- Gottlob, H. D. B., et al.
(författare)
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Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics
- 2009
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 86:7-9, s. 1642-1645
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Tidskriftsartikel (refereegranskat)abstract
- We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high-k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd2O3) from a silicon oxide (SiO2) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). (C) 2009 Elsevier B.V. All rights reserved.
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| 3. |
- Welch, C. C., et al.
(författare)
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Silicon etch process options for micro- and nanotechnology using inductively coupled plasmas
- 2006
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 83:4-9, s. 1170-1173
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Tidskriftsartikel (refereegranskat)abstract
- Silicon is an essential material in the fabrication of a continually expanding range of micro- and nano-scale opto-and microelectronic devices. The fabrication of many such devices requires patterning of the silicon but until recently exploitation of the technology has been restricted by the difficulty of forming the ever-smaller features and higher aspect ratios demanded. Plasma etching through a mask layer is a very useful means for fine-dimension patterning of silicon. In this work, several solutions are presented for the micro- and nano-scale etching of silicon using inductively coupled plasmas ICP.
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| 4. |
- Bell, David C., et al.
(författare)
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Precision material modification and patterning with He ions
- 2009
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Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 27:6, s. 2755-2758
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Tidskriftsartikel (refereegranskat)abstract
- The authors report on the use of a helium ion microscope as a potential technique for precise nanopatterning. Combined with an automated pattern generation system, they demonstrate controlled etching and patterning of materials, giving precise command over the geometery of the modified nanostructure. After the determination of suitable doses, sharp edge profiles and clean etching of areas in materials were observed. In this article they present examples of patterning on SiO(2) and graphene, which is particularly relevant. This technique could be an avenue for precise material modification for future graphene based device fabrication. The technique has the potential to revolutionize the way that very thin, one-atomic layer materials are modified in a controlled and predictable way.
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| 5. |
- Benetti, M., et al.
(författare)
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POLYSILICON MESOSCOPIC WIRES COATED BY Pd AS H(2) SENSORS
- 2009
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Ingår i: PROCEEDINGS OF THE 13TH ITALIAN CONFERENCE ON SENSORS AND MICROSYSTEMS. - SINGAPORE : WORLD SCIENTIFIC PUBL CO PTE LTD. ; , s. 161-165
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Konferensbidrag (refereegranskat)abstract
- In this work a novel monocrystalline silicon nanowires array has been investigated and presented as hydrogen sensor, designed and fabricated by employing high resolution microfabrication techniques and featuring a high surface/volume ratio. The nanowires arrays makes up the channel of a MOS system, palladium-silicon dioxide-silicon. Several devices have been fabricated by using a SOI (Silicon On Insulator) substrate, Source and Drain have been geometrically patterned by optical lithography and Boron p-doped. Electron Beam Litography (EBL) defined the MOS channel made up of a nanowires array of different length and width in different transistors. The pads of Source and Drain have been manufactured with an aluminium film deposition. The Gate has been fabricated with a grown silicon oxide layer (17.4 nm) and Palladium has been used as gate contact. Polarizing and exposing the device to H(2)/N(2) cycles at different concentrations some preliminary measurements have been successfully conducted.
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| 6. |
- Fuchs, A., et al.
(författare)
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Nanowire fin field effect transistors via UV-based nanoimprint lithography
- 2006
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Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 24:6, s. 2964-2967
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Tidskriftsartikel (refereegranskat)abstract
- A triple step alignment process for UV nanoimprint lithography (UV-NIL) for the fabrication of nanoscale fin field effect transistors (FinFETs) is presented. An alignment accuracy is demonstrated between two functional layers of less than 20 nm (3 sigma). The electrical characterization of the FinFETs fabricated by a full NIL process demonstrates the potential of UV-NIL for future nanoelectronic devices.
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| 7. |
- Lemme, Max C., 1970-, et al.
(författare)
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Etching of Graphene Devices with a Helium Ion Beam
- 2009
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Ingår i: ACS Nano. - : American Chemical Society (ACS). - 1936-0851 .- 1936-086X. ; 3:9, s. 2674-2676
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Tidskriftsartikel (refereegranskat)abstract
- We report on the etching of graphene devices with a helium ion beam, including in situ electrical measurement during lithography. The etching process can be used to nanostructure and electrically isolate different regions In a graphene device, as demonstrated by etching a channel in a suspended graphene device with etched gaps down to about 10 nm. Graphene devices on silicon dioxide (02) substrates etch with lower He ion doses and are found to have a residual conductivity after etching, which we attribute to contamination by hydrocarbons.
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| 8. |
- Lemme, Max C., 1970-, et al.
(författare)
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Highly selective HBr etch process for fabrication of Triple-Gate nano-scale SOI-MOSFETs
- 2004
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Ingår i: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 73-74:SI, s. 346-350
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Tidskriftsartikel (refereegranskat)abstract
- New three-dimensional device concepts are considered necessary for the ultimate scaling of the gate length of metal-oxide-semiconductor field effect transistors (MOSFETs). Both Triple-Gate field effect transistors and FinFETs require a gate etch process with excellent selectivity over the gate oxide material. In this work, a highly selective, anisotropic gate etch process using HBr and O-2 as the reactive gases in an inductively coupled plasma reactive ion etch tool is described. Polysilicon thickness measurements have been taken to calculate etch rate and uniformity. Polysilicon wafers for each experimental condition were given different overetch times and SiO2 losses were plotted against time, with the gradient yielding the SiO2 etch rate. The optimized etch process yields excellent results for nanoscale polysilicon gates.
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| 9. |
- Lemme, Max C., 1970-, et al.
(författare)
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Triple-gate metal-oxide-semiconductor field effect transistors fabricated with interference lithography
- 2004
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Ingår i: Nanotechnology. - : IOP Publishing. - 0957-4484 .- 1361-6528. ; 15:4, s. S208-S210
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Tidskriftsartikel (refereegranskat)abstract
- In this work, n-type triple-crate metal-oxide-semiconductor field effect transistors (MOSFETs) are presented, where laser interference lithography (LIL) is integrated into a silicon-on-insulator (SOI) CMOS process to provide for the critical definition of the transistor channels. A mix and match process of optical contact lithography and LIL is developed to achieve device relevant structures. The triple-gate MOSFETs are electrically characterized to demonstrate the feasibility of this low cost fabrication process.
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| 10. |
- Abermann, S., et al.
(författare)
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Comparative study on the impact of TiN and Mo metal gates on MOCVD-grown HfO2 and ZrO2 high-kappa dielectrics for CMOS technology
- 2007
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Ingår i: Physics of Semiconductors, Pts A and B. - : AIP. - 9780735403970 ; , s. 293-294
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Konferensbidrag (refereegranskat)abstract
- We compare metal oxide semiconductor capacitors, investigating Titanium-Nitride and Molybdenum as gate materials, as well as metal organic chemical vapor deposited ZrO2 and HfO2 as high-kappa dielectrics, respectively. The impact of different annealing steps on the electrical characteristics of the various gate stacks is a further issue. The positive effect of post metallization annealing in forming gas atmosphere as well as observed mid-gap pinning of TiN and Mo metal gates is presented.
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