| 1. |
- Liu, Lizheng, et al.
(författare)
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A Design of Autonomous Error-Tolerant Architectures for Massively Parallel Computing
- 2018
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1063-8210 .- 1557-9999. ; 26:10, s. 2143-2154
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Tidskriftsartikel (refereegranskat)abstract
- The massively parallel computing systems composed of many processors are connected on chips, which will become more and more complex and unreliable. This paper presents an error-tolerant design based on the autonomous error-tolerant (AET) architecture that aims to have a self-repairing capability. A nearby error sensing mechanism is designed to discover faults, and an active evolution scheme is studied to handle unrecoverable errors. A circuit backup switching mechanism is proposed to bypass the failed nodes. The board-level prototype is implemented based on dual-core embedded processors. The analysis shows that the error-tolerant capability of the proposed architecture is better than the conventional multimodular redundant system when the failure rate of a single core is less than 0.7. In the AET test system consisting of 16 processors, the error-tolerant capability is verified. The results show that the relative variation of the overall performance of the AET system will not be changed due to the high reliability requirements of the system. Through experimental comparison, under the premise that the architecture of AET and the triple modular redundancy method are basically consistent in reliability, whether on the logical-level error tolerant or on the physical-level error tolerant, the former has lower power consumption.
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| 2. |
- Huang, Boming, et al.
(författare)
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IECA : An In-Execution Configuration CNN Accelerator With 30.55 GOPS/mm(2) Area Efficiency
- 2021
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 68:11, s. 4672-4685
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Tidskriftsartikel (refereegranskat)abstract
- It remains challenging for a Convolutional Neural Network (CNN) accelerator to maintain high hardware utilization and low processing latency with restricted on-chip memory. This paper presents an In-Execution Configuration Accelerator (IECA) that realizes an efficient control scheme, exploring architectural data reuse, unified in-execution controlling, and pipelined latency hiding to minimize configuration overhead out of the computation scope. The proposed IECA achieves row-wise convolution with tiny distributed buffers and reduces the size of total on-chip memory by removing 40% of redundant memory storage with shared delay chains. By exploiting a reconfigurable Sequence Mapping Table (SMT) and Finite State Machine (FSM) control, the chip realizes cycle-accurate Processing Element (PE) control, automatic loop tiling and latency hiding without extra time slots for pre-configuration. Evaluated on AlexNet and VGG-16, the IECA retains over 97.3% PE utilization and over 95.6% memory access time hiding on average. The chip is designed and fabricated in a UMC 55-nm process running at a frequency of 250 MHz and achieves an area efficiency of 30.55 GOPS/mm(2) and 0.244 GOPS/KGE (kilo-gate-equivalent), which makes an over 2.0x and 2.1x improvement, respectively, compared with that of previous related works. Implementation of the IEC control scheme uses only a 0.55% area of the 2.75 mm(2) core.
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| 3. |
- Li, Yibei, 1993-, et al.
(författare)
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Robust formation control for unicycle robots with directional sensor information
- 2023
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Ingår i: Autonomous Intelligent Systems. - : Springer Nature. - 2730-616X. ; 3:1
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, the formation control problem for a multi-agent system is studied. Two new robust control algorithms for serial and parallel formations respectively are proposed, which take the constraints of limited field of view into consideration. Without the need for any global information, the only relative information required is distance and bearing angle, thus is easy to implement with onboard directional sensors. It is then demonstrated how complex formations can be realized by combining the proposed basic controllers. Finally, effectiveness of the proposed algorithms is illustrated by numerical examples.
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| 4. |
- Liu, Lizheng, et al.
(författare)
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A FPGA-based Hardware Accelerator for Bayesian Confidence Propagation Neural Network
- 2020
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Ingår i: 2020 IEEE Nordic Circuits and Systems Conference, NORCAS 2020 - Proceedings. - : Institute of Electrical and Electronics Engineers (IEEE).
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Konferensbidrag (refereegranskat)abstract
- The Bayesian Confidence Propagation Neural Network (BCPNN) has been applied in higher level of cognitive intelligence (e.g. working memory, associative memory). However, in the spike-based version of this learning rule the pre-, postsynaptic and coincident activity is traced in three low-passfiltering stages, the calculation processes of weight update are very computationally intensive. In this paper, a hardware architecture of the updating process for lazy update mode is proposed for updating 8 local synaptic state variables. The parallelism by decomposing the calculation steps of formulas based on the inherent data dependencies is optimized. The FPGA-based hardware accelerator of BCPNN is designed and implemented. The experimental results show the updating process on FPGA can be accomplished within 110 ns with a clock frequency of 200 MHz, the updating speed is greatly enhanced compared with the CPU test. The trade-off between performance, accuracy and resources on dedicated hardware is evaluated, and the impact of the module reuse on resource consumption and computing performance is evaluated.
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| 5. |
- Liu, Lizheng, et al.
(författare)
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An Autonomous Error-Tolerant Architecture Featuring Self-reparation for Convolutional Neural Networks
- 2020
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Ingår i: Proceeding of the IEEE Vehicular Technology Conference. - : Institute of Electrical and Electronics Engineers (IEEE).
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Konferensbidrag (refereegranskat)abstract
- Convolutional neural networks are widely used in artificial intelligence and Internet of Things area. As the scale of convolutional neural network expands, more and more processing units are provided for it. The systems are easy prone to error, and any computing problems in any layer of the network will lead to wrong output results. Traditional multimode redundancy methods make the systems more complex, and increase power consumption. This paper proposes an autonomous error-tolerant architecture for convolutional neural networks. Taking the LeNet-5 as an example, the network layers of CNN are mapped on the AET architecture, an error-tolerant synapse is designed to discover the errors, an active evolution scheme is designed to handle unrecoverable errors and implement network reconfiguration. This design is implemented on FPGA, and the experimental results show that this architecture can realize effective error tolerance for convolutional neural network and has fast error recovery ability under the premise of ensuring the same recognition accuracy.
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| 6. |
- Wang, Yuhan, et al.
(författare)
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Robust Robot Formation Control Based on Streaming Communication and Leader-Follower Approach
- 2024
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Ingår i: 20th International Wireless Communications and Mobile Computing Conference, IWCMC 2024. - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 567-572
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Konferensbidrag (refereegranskat)abstract
- In this paper, a non-visual robotic formation control method based on a streaming communication architecture and a leader-follower control model is studied. The proposed stream-based communication architecture is inspired by the flocking behavior of fish. We analogize it into a form resembling an N-ary tree for communication purposes. Communication proceeds to the next layer only when all nodes in the upper layer have completed the follower selection. We also introduce a fault-tolerance mechanism and a termination filtering mechanism to prevent multiple leaders from choosing the same follower, avoiding a scenario where the robots in the last layer enter an endless loop of follower selection. The proposed stream-based communication architecture, built upon serial and parallel tracking, can achieve more complex formations, such as rectangular formations, closely resembling real-world scenarios, significantly enhancing formation efficiency. Simulation experiments on the e-puck platform validate the effectiveness and robustness of this architecture.
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| 7. |
- Xu, Jianqiang, et al.
(författare)
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Design of Smart Unstaffed Retail Shop Based on IoT and Artificial Intelligence
- 2020
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Ingår i: IEEE Access. - : Institute of Electrical and Electronics Engineers (IEEE). - 2169-3536. ; 8, s. 147728-147737
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Tidskriftsartikel (refereegranskat)abstract
- Unstaffed retail shops have emerged recently and been noticeably changing our shopping styles. In terms of these shops, the design of vending machine is critical to user shopping experience. The conventional design typically uses weighing sensors incapable of sensing what the customer is taking. In the present study, a smart unstaffed retail shop scheme is proposed based on artificial intelligence and the internet of things, as an attempt to enhance the user shopping experience remarkably. To analyze multiple target features of commodities, the SSD (300x300) algorithm is employed; the recognition accuracy is further enhanced by adding sub-prediction structure. Using the data set of 18, 000 images in different practical scenarios containing 20 different type of stock keeping units, the comparison experimental results reveal that the proposed SSD (300x300) model outperforms than the original SSD (300x300) in goods detection, the mean average precision of the developed method reaches 96.1% on the test dataset, revealing that the system can make up for the deficiency of conventional unmanned container. The practical test shows that the system can meet the requirements of new retail, which greatly increases the customer flow and transaction volume.
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