| 1. |
- Huang, Daming, et al.
(författare)
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A Modified Charge-Pumping Method for the Characterization of Interface-Trap Generation in MOSFETs
- 2009
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 56:2, s. 267-274
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Tidskriftsartikel (refereegranskat)abstract
- A novel recovery-free interface-trap measurement method is presented in detail. This method is the modification of the conventional charge pumping (CP) by extending the pulse low level to the stress-bias and minimizing the pulse high-level duty cycle to suppress the recovery effect. The method is applied to study the negative-bias temperature instability in p-MOSFETs. As compared with the conventional CP, a much larger interface-trap generation under stress is observed by the new method. A power law time dependence (similar to t(n)) of interface-trap generation is observed. The index n. is less than that derived from conventional CP and increases with temperature, demonstrating a dispersive process involved in the trap generation dynamics.
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| 2. |
- Li, Jiantong, et al.
(författare)
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Ink-jet printed thin-film transistors with carbon nanotube channels shaped in long strips
- 2011
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Ingår i: Journal of Applied Physics. - : AIP Publishing. - 0021-8979 .- 1089-7550. ; 109:8, s. 084915-
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Tidskriftsartikel (refereegranskat)abstract
- The present work reports on the development of a class of sophisticated thin-film transistors (TFTs) based on ink-jet printing of pristine single-walled carbon nanotubes (SWCNTs) for the channel formation. The transistors are manufactured on oxidized silicon wafers and flexible plastic substrates at ambient conditions. For this purpose, ink-jet printing techniques are developed with the aim of high-throughput production of SWCNT thin-film channels shaped in long strips. Stable SWCNT inks with proper fluidic characteristics are formulated by polymer addition. The present work unveils, through Monte Carlo simulations and in light of heterogeneous percolation, the underlying physics of the superiority of long-strip channels for SWCNT TFTs. It further predicts the compatibility of such a channel structure with ink-jet printing, taking into account the minimum dimensions achievable by commercially available printers. The printed devices exhibit improved electrical performance and scalability as compared to previously reported ink-jet printed SWCNT TFTs. The present work demonstrates that ink-jet printed SWCNT TFTs of long-strip channels are promising building blocks for flexible electronics.
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| 3. |
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| 4. |
- Liu, Zhiying, et al.
(författare)
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Hysteresis-free thin-film transistors achieved by novel solution-processing of nanotubes/polymer composites
- 2012
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Ingår i: Materials Research Society Spring Meeting 2012, San Francisco, April 9-13, 2012..
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Konferensbidrag (refereegranskat)abstract
- Thin-film transistors (TFTs) based on single-walled carbon nanotubes (SWCNTs) have gained enormous attention in the community of flexible/stretchable electronics. At present, such TFTs often suffer from severe problems including giant hysteresis in their transfer characteristics. With SiO2 as the gate dielectric, extensive investigations have led to generally accepted understanding of the hysteresis as being caused by charge transfer between the SWCNTs and their surroundings including both water molecules bound on the SiO2 surface (Si≡OH) and the water/oxygen molecules in the ambient atmosphere. In order to combat the hysteresis issue, significant efforts have been made by annealing the TFTs in vacuum and separating SWCNTs from SiO2 by deposition of a self-assembled monolayer (SAM) on the SiO2 or passivating the SWCNTs with an organic or inorganic dielectric film. These methods, however, require either processing in inert environment or developing elaborated processes. In the present work, we demonstrate hysteresis-free TFTs based on SWCNT/polymer composite without any complex treatment. The composite consists of SWCNTs and poly-9,9_dioctyl-fluorene-co-bithiophene (F8T2). With the aid of polymer F8T2, SWCNTs can be efficiently dissolved in commonly used solvents thereby forming a uniform composite solution. By soaking a chip with predefined TFT structures on an oxidized Si substrate in the composite solution, direct assembly of the composite on the SiO2 occurs, leading to the formation of a composite thin film in the channel region of the TFTs. Although fabricated using a very simple process, our TFTs exhibit hysteresis-free operation under ambient conditions. It is plausible to suggest that SWCNTs are embedded in the F8T2 matrix with the latter providing an effective shield for the former against the trap sites on the SiO2 and the H2O/O2 molecules in the atmosphere. In comparison to the other reported means aiming at hysteresis reduction, the present method is simple, robust, solution processable, effective, and operable under ambient conditions. In addition, we have found F8T2 to preferentially disperse semiconducting SWCNTs rendering a selective removal of the metallic species in the solution. This selectivity is of paramount importance as it results in high-performance TFTs with both high on-state current (0.1 µA/µm @ channel length = 50 µm) and large on/off current ratio (103-105). The TFTs have also shown significantly improved uniformity and dimensional scalability with a mobility value of 10-20 cm2V-1s-1, which have allowed us to investigate the TFTs using the resultant logic circuits.
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| 5. |
- Liu, Zhiying, et al.
(författare)
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Mobility Extraction for Nanotube TFTs
- 2011
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Ingår i: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 32:7, s. 913-915
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Tidskriftsartikel (refereegranskat)abstract
- An extensive investigation of carrier mobility is presented for thin-film transistors (TFTs) with single-walled carbon nanotube (SWCNT) networks as the semiconductor channel. For TFTs particularly with low-density SWCNTs in the networks, the extracted mobility using the standard method for Si metal-oxide-semiconductor field-effect transistors is erroneous, mainly resulting from use of a parallel-plate capacitor model and assumption of the source-drain current being inversely proportional to the channel length. Large hysteresis in the transfer characteristics further complicates the extraction. By properly addressing all these challenges in this letter, a comprehensive methodology is established, leading to the extraction of mobility values that are independent of geometrical parameters.
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| 6. |
- Liu, Zhiying, et al.
(författare)
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On Gate Capacitance of Nanotube Networks
- 2011
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Ingår i: IEEE Electron Device Letters. - : IEEE. - 0741-3106 .- 1558-0563. ; 32:5, s. 641-643
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Tidskriftsartikel (refereegranskat)abstract
- This letter presents a systematic investigation of the gate capacitance C-G of thin-film transistors (TFTs) based on randomly distributed single-walled carbon nanotubes (SWCNTs) in the channel. In order to reduce false counting of SWCNTs that do not contribute to current conduction, C-G is directly measured on the TFTs using a well-established method for MOSFETs. Frequency dispersion of C-G is observed, and it is found to depend on the percolation behavior in SWCNT networks. This dependence can be accounted for using an RC transmission line model. These results are of important implications for the determination of carrier mobility in nanoparticle-based TFTs.
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| 7. |
- Liu, Zhiying, et al.
(författare)
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SMALL-Hysteresis Thin-Film Transistors Achieved by Facile Dip-Coating of Nanotube/Polymer Composite
- 2012
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Ingår i: Advanced Materials. - : Wiley. - 0935-9648 .- 1521-4095. ; 24:27, s. 3633-3638
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Tidskriftsartikel (refereegranskat)abstract
- Small-hysteresis, high-performance thin-film transistors (TFTs) are readily realized simply by dip-coating of a solution-processable composite. The composite consists of single-walled carbon nanotubes (SWCNTs) embedded in semiconducting polymer used as the channel material. The resultant TFTs simultaneously exhibit large on/off current ratio, high on-current level, high mobility in the range 10−20 cm2V−1s−1, and good uniformity and scalability.
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| 8. |
- Liu, Zhiying, et al.
(författare)
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Solution-Processable Nanotube/Polymer Composite for High-Performance TFTs
- 2011
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Ingår i: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 32:9, s. 1299-1301
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Tidskriftsartikel (refereegranskat)abstract
- Thin-film field-effect transistors (TFTs) are readily fabricated using a semiconductor composite that is solution processed under ambient conditions for the conduction channel. The composite comprises single-walled carbon nanotubes (SWCNTs) embedded in poly-9,9' dioctyl-fluorene-co-bithiophene. Carrier mobility values approaching 10 cm(2)V(-1)s(-1) are obtained for the composite with relatively high SWCNT concentrations. When the SWCNT concentration is reduced for a large ON/OFF current ratio > 10(6), the mobility remains decent around 0.3 cm(2)V(-1)s(-1). The resultant TFTs display remarkable environmental and operational reliability. Nanotube-based composites are therefore of significance in printed electronics owing to their simplicity in device fabrication and competitiveness in device performance.
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| 9. |
- Liu, Zhiying, 1982-, et al.
(författare)
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Solution-Processed Logic Gates Based On Nanotube/Polymer Composite
- 2013
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 60:8, s. 2542-2547
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Tidskriftsartikel (refereegranskat)abstract
- Hysteresis-free logic gates capable of operation at 100 kHz are fabricated basing on local-gate thin-film transistors with their channel featuring solution-processed composite films of single-walled carbon nanotubes (SWCNTs) and poly(9,9-dioctylfluorene-co-bithiophene) (F8T2). Using dip-coating for deposition of composite films, high-density SWCNTs are found to be embedded in an F8T2 layer and thus being kept from the underlying AlOx gate dielectric by a certain distance. The presence of the F8T2 interlayer effectively suppresses hysteresis although it also weakens the gate electrostatic control. The fabricated transistors are characterized by nil hysteresis, high carrier mobility, large ON/OFF current ratio, low operation voltage, small subthreshold swing, and remarkable scalability. These properties are crucial for the realization of the well-performing logic circuits.
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| 10. |
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