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| 2. |
- Hållstedt, Julius, et al.
(author)
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Leakage current reduction in 80 nm biaxially strained Si nMOSFETs on in-situ doped SiGe virtual substrates
- 2007
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In: ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference 2008. - 9781424411238 ; , s. 319-322
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Conference paper (peer-reviewed)abstract
- We present a comprehensive study of biaxially strained (up to similar to 3 GPa stress) Si nMOSFETs down to 80 nm gatelength. Well behaved 80 nm devices with expected strain-induced electrical enhancement were demonstrated. Special emphasis was put on investigation of substrate junction leakage and source to drain leakage. In-situ doped wells and channel profiles demonstrated superior substrate junction leakage for the relaxed SiGe substrates compared to conventional implantation. The source to drain leakage in 80 nm devices was effectively reduced by increment of channel doping and rotation of the channel direction.
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| 4. |
- Ni, Wei-Xin, et al.
(author)
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X-ray reciprocal space mapping studies of strain relaxation in thin SiGe layers (=100 nm) using a low temperature growth step
- 2001
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In: Journal of Crystal Growth. - 0022-0248 .- 1873-5002. ; 227-228, s. 756-760
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Conference paper (other academic/artistic)abstract
- Relaxation of thin SiGe layers (~90 nm) grown by molecular beam epitaxy using a low temperature growth step (120-200°C) has been investigated using two-dimensional reciprocal space mapping of X-ray diffraction. The samples studied have been divided in two groups, depending on the substrate cooling process during the growth of the low temperature layer. It has been found that a higher degree of relaxation was easily achieved for the sample group without growth interruption. A process window for full relaxation of the Si0.74Ge0.26 layer has been observed in the range of 140-150°C. © 2001 Elsevier Science B.V.
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| 5. |
- Olsen, S. H., et al.
(author)
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Strained Si/SiGe MOS technology : Improving gate dielectric integrity
- 2009
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In: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 86:3, s. 218-223
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Journal article (peer-reviewed)abstract
- Strained Si is recognised as a necessary technology booster for the nanoelectronics regime. This work shows that high levels of stress attainable from globally strained Si/SiGe platforms can benefit gate leakage and reliability in addition to MOSFET channel mobility. Device self-heating due to the low thermal conductivity of SiGe is shown to be the dominating factor behind compromised performance against short channel strained Si/SiGe MOSFETs. Novel thin virtual substrates aimed at reducing self-heating effects are investigated. In addition to reducing self-heating effects, the thin Virtual substrates provide further improvements to gate oxide integrity, reliability and lifetime compared with conventional thick virtual substrates. This is attributed to tire lower surface roughness of the thin virtual substrates which arises due to the reduced interactions of strain-relieving misfit dislocations during thin Virtual substrate growth. Good agreement between experimental data and physical models is demonstrated, enabling gate leakage mechanisms to be identified. The advantages and challenges of using globally strained Si/SiGe to advance MOS technology are discussed.
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| 6. |
- O'Neill, A.G., et al.
(author)
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Strained silicon technology
- 2007
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In: ICSICT-2006. - 1424401615 - 9781424401611 ; , s. 104-107
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Conference paper (peer-reviewed)abstract
- Following a brief review of strained silicon technology options, this paper presents results and analysis of strained Si n-channel MOSFETs fabricated on thin SiGe virtual substrates. Significant improvements in electrical performance are demonstrated compared with Si control devices. The impact of SiGe device self-heating is compared for strained Si MOSFETs fabricated on thin and thick virtual substrates. The work demonstrates that by using high quality thin virtual substrates the compromised performance enhancements commonly observed in short gate length MOSFETs and high bias conditions due to self-heating in conventional thick virtual substrate devices are eradicated.
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| 7. |
- O'Neill, A., et al.
(author)
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Reduced self-heating by strained silicon substrate engineering
- 2008
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In: Applied Surface Science. - : Elsevier BV. - 0169-4332 .- 1873-5584. ; 254:19, s. 6182-6185
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Journal article (peer-reviewed)abstract
- Substrate engineering innovations such as SOI and the use of Si/SiGe virtual substrates become necessary in order to maintain performance leverage of integrated circuits with continued scaling. The relevance of thermal effects in device design increases since the thermal conductivity of these new materials is poor. The electrical performance of devices fabricated on thin virtual substrates grown by two different techniques is presented. It is found that self-heating is reduced and that thermal resistance measurements agree with modelling predictions. The reduction in performance enhancement seen in many strained Si MOSFETs is found here to be largely due to self-heating effects, rather than parasitics or the loss of strain.
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| 8. |
- von Haartman, M., et al.
(author)
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Impact of strain and channel orientation on the low-frequency noise performance of Si n- and pMOSFETs
- 2007
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In: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 51:5, s. 771-777
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Journal article (peer-reviewed)abstract
- Mobility and low-frequency (LF) noise were studied in tensile strained Si n- and pMOSFETs fabricated on relaxed SiGe virtual substrates. Both the impact of the channel orientation ((110) or (100) on (100) Si) and the tensile strain were carefully investigated. Two types of virtual substrates were used; a thin relaxed SiGe layer (20% Ge) and a thick one (27% Ge). The strained Si nMOSFETs fabricated on the thin substrate showed similar LF noise level as in the reference devices, whereas the thick substrate caused severely increased LF noise in the nMOSFETs. The latter was linked to the higher Ge concentration and explained by possible misfit dislocations and increased defect densities, likely resulting from strain relaxation caused by ion implantation damage. On the other hand, considerably lower LF noise was achieved in the pMOSFETs on the thick SiGe. The channel orientation was not found to have a significant influence on the LF noise performance in any of the studied devices.
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