| 1. |
- Mahdavi, Mojtaba, et al.
(författare)
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A Low Complexity Massive MIMO Detection Scheme Using Angular-Domain Processing
- 2018
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Ingår i: IEEE Global Conference on Signal and Information Processing (GlobalSIP). - 9781728112961 - 9781728112954 ; , s. 181-185
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Konferensbidrag (refereegranskat)abstract
- Signal processing complexity and required memory become problematic in massive MIMO systems as the dimension of channel state information (CSI) matrix grows significantly with the large number of antennas and users. To address these challenges, we propose the first angular-domain massive MIMO detection scheme, which is based on three concepts: transferring the baseband processing from the spatial domain to the angular domain; exploiting the sparsity of received beams to reduce the dimension of CSI matrix; and performing the whole detection and precoding in the angular domain using the reduced CSI matrix. We have measured the massive MIMO channel at 2.6 GHz with a 128-antenna linear array communicating with 16 users to evaluate our scheme. Complexity analysis and simulations show that proposed idea leads to 40% – 70% reduction in the processing complexity and memory without significant performance loss, which significantly outperforms the antenna-domain schemes.
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| 2. |
- Mahdavi, Mojtaba, et al.
(författare)
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A low latency and area efficient FFT processor for massive MIMO systems
- 2017
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Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS), 2017 - Proceedings. - 9781509014279 - 9781467368537 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- A low-latency and area-efficient FFT/IFFT scheme is presented. The main idea is to utilize OFDM guard bands to reduce the operation counts and processing time, which results in 42% latency reduction compared to the reported pipelined schemes. To realize this idea, a modified pipelined architecture and an efficient data scheduling scheme are proposed. Furthermore, the proposed architecture is scalable to different FFT sizes and is also reconfigurable to support a wide range of applications. A 2048-point FFT/IFFT processor based on the proposed scheme has been designed, resulting in 1200 clock cycles latency, which can address the low latency demand of massive MIMO systems. Synthesis results in a 28 nm CMOS technology show that proposed design attains a throughput of 1 GS/s when clocked at 500 MHz.
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| 3. |
- Mahdavi, Mojtaba, et al.
(författare)
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A Low Latency FFT/IFFT Architecture for Massive MIMO Systems Utilizing OFDM Guard Bands
- 2019
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Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1558-0806. ; 66:7, s. 2763-2774
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Tidskriftsartikel (refereegranskat)abstract
- A considerable part of latency in the baseband of massive multiple-input multiple-output (MIMO) systems is introduced by orthogonal frequency division multiplexing (OFDM) (de)modulation. To address the low-latency demand of massive MIMO systems, a fast Fourier transform (FFT) processor and corresponding reordering scheme are proposed, which reduce the processing latency and reordering latency of OFDM-based systems, respectively. The main idea is to utilize the OFDM guard bands to decrease the number of required computations and thus the processing time. In case of a 2048-point IFFT, the proposed scheme leads to 42% reduction in latency compared to the reported pipelined schemes at the cost of 4% additional memory, which is around 2.4% of the total chip area. To realize this idea, a modified pipelined architecture with a reorganized memory structure and also an efficient data scheduling mechanism for memories and butterflies are developed. Using the proposed scheme, a 2048-point FFT/IFFT processor has been implemented in a 28 nm complementary metal-oxide-semiconductor technology. The post-layout simulations show that our design achieves a throughput of 0.6 GS/s and 1200 clock cycles latency, the lowest latency reported to-date for single-input pipelined FFT/IFFT architectures.
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| 4. |
- Mahdavi, Mojtaba, et al.
(författare)
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A VLSI Implementation of Angular-Domain Massive MIMO Detection
- 2019
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Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS) 2019 - Proceedings. - 9781728103976 - 9781728103983 ; , s. 1-5
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Konferensbidrag (refereegranskat)abstract
- This paper presents an angular-domain massive MIMO detector which exploits sparsity in massive MIMO channel along with a reconfigurable systolic array architecture to achieve high area efficiency. The underlying idea is to perform signal detection in the angular domain, where the channel matrix can have much lower dimension due the limited number of dominant angles (of arrival and departure) of the wireless signal. Evaluated using the measured massive MIMO channel, the proposed method results in 40%-70% reduction in processing complexity and memory requirements compared to traditional antenna-domain detection. This complexity reduction enables extensive hardware reuse where all the operations of detection processing are mapped to a condensed reconfigurable systolic array. The angular-domain zero-forcing detector, which supports 128 base station antennas and 16 users is implemented in a 28 nm FD-SOI technology. Synthesis result shows that our design attains a throughput of 510 MSps with an area of 537 kG.
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| 5. |
- Mahdavi, Mojtaba, et al.
(författare)
-
Angular-Domain Massive MIMO Detection
- 2021
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Ingår i: ; , s. 1-5
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Konferensbidrag (refereegranskat)abstract
- In massive multiple-input multiple-output (MIMO) systems, the large size of channel state information (CSI) matrix significantly increases the computational complexity of uplink detection and size of required memory to store the channel data. To address these challenges, we propose to perform detection in the angular domain, where the channel information can be presented in a more condensed way. The underlying idea is to exploit the sparsity of massive MIMO channel in the angular domain to reduce the size of CSI matrix by selecting dominant beams. Then, an angular-domain linear detector followed by a non-linear post-processing scheme is proposed to perform detection using the reduced-size CSI. Evaluated using measured massive MIMO channels, our method results in 35%-73% reduction in complexity and required memory compared to traditional detectors while it achieves better performance. Moreover, this paper provides a framework, which trades between performance, complexity, and size of required memory. As a proof of concept, we implement the angular-domain detector in a 28 nm FD-SOI CMOS for a massive MIMO with 128 antennas communicating with up to 16 users. Synthesis result shows that our design attains a throughput of 2240 Mbps with an area of 829 k gates.
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| 6. |
- Mahdavi, Mojtaba, et al.
(författare)
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Angular-Domain Massive MIMO Detection: Algorithm, Implementation, and Design Tradeoffs
- 2020
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Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1558-0806. ; 67:6, s. 1948-1961
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Tidskriftsartikel (refereegranskat)abstract
- In massive multiple-input multiple-output (MIMO) systems, the large size of channel state information (CSI) matrix significantly increases the computational complexity of uplink detection and size of required memory to store the channel data. To address these challenges, we propose to perform detection in the angular domain, where the channel information can be presented in a more condensed way. The underlying idea is to exploit the sparsity of massive MIMO channel in the angular domain to reduce the size of CSI matrix by selecting dominant beams. Then, an angular-domain linear detector followed by a non-linear post-processing scheme is proposed to perform detection using the reduced-size CSI. Evaluated using measured massive MIMO channels, our method results in 35%-73% reduction in complexity and required memory compared to traditional detectors while it achieves better performance. Moreover, this paper provides a framework, which trades between performance, complexity, and size of required memory. As a proof of concept, we implement the angular-domain detector in a 28 nm FD-SOI CMOS for a massive MIMO with 128 antennas communicating with up to 16 users. Synthesis result shows that our design attains a throughput of 2240 Mbps with an area of 829 k gates.
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| 7. |
- Mahdavi, Mojtaba
(författare)
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Baseband Processing for 5G and Beyond: Algorithms, VLSI Architectures, and Co-design
- 2021
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- In recent years the number of connected devices and the demand for high data-rates have been significantly increased. This enormous growth is more pronounced by the introduction of the Internet of things (IoT) in which several devices are interconnected to exchange data for various applications like smart homes and smart cities. Moreover, new applications such as eHealth, autonomous vehicles, and connected ambulances set new demands on the reliability, latency, and data-rate of wireless communication systems, pushing forward technology developments. Massive multiple-input multiple-output (MIMO) is a technology, which is employed in the 5G standard, offering the benefits to fulfill these requirements. In massive MIMO systems, base station (BS) is equipped with a very large number of antennas, serving several users equipments (UEs) simultaneously in the same time and frequency resource. The high spatial multiplexing in massive MIMO systems, improves the data rate, energy and spectral efficiencies as well as the link reliability of wireless communication systems. The link reliability can be further improved by employing channel coding technique. Spatially coupled serially concatenated codes (SC-SCCs) are promising channel coding schemes, which can meet the high-reliability demands of wireless communication systems beyond 5G (B5G). Given the close-to-capacity error correction performance and the potential to implement a high-throughput decoder, this class of code can be a good candidate for wireless systems B5G. In order to achieve the above-mentioned advantages, sophisticated algorithms are required, which impose challenges on the baseband signal processing. In case of massive MIMO systems, the processing is much more computationally intensive and the size of required memory to store channel data is increased significantly compared to conventional MIMO systems, which are due to the large size of the channel state information (CSI) matrix. In addition to the high computational complexity, meeting latency requirements is also crucial. Similarly, the decoding-performance gain of SC-SCCs also do come at the expense of increased implementation complexity. Moreover, selecting the proper choice of design parameters, decoding algorithm, and architecture will be challenging, since spatial coupling provides new degrees of freedom in code design, and therefore the design space becomes huge. The focus of this thesis is to perform co-optimization in different design levels to address the aforementioned challenges/requirements. To this end, we employ system-level characteristics to develop efficient algorithms and architectures for the following functional blocks of digital baseband processing. First, we present a fast Fourier transform (FFT), an inverse FFT (IFFT), and corresponding reordering scheme, which can significantly reduce the latency of orthogonal frequency-division multiplexing (OFDM) demodulation and modulation as well as the size of reordering memory. The corresponding VLSI architectures along with the application specific integrated circuit (ASIC) implementation results in a 28 nm CMOS technology are introduced. In case of a 2048-point FFT/IFFT, the proposed design leads to 42% reduction in the latency and size of reordering memory. Second, we propose a low-complexity massive MIMO detection scheme. The key idea is to exploit channel sparsity to reduce the size of CSI matrix and eventually perform linear detection followed by a non-linear post-processing in angular domain using the compressed CSI matrix. The VLSI architecture for a massive MIMO with 128 BS antennas and 16 UEs along with the synthesis results in a 28 nm technology are presented. As a result, the proposed scheme reduces the complexity and required memory by 35%–73% compared to traditional detectors while it has better detection performance. Finally, we perform a comprehensive design space exploration for the SC-SCCs to investigate the effect of different design parameters on decoding performance, latency, complexity, and hardware cost. Then, we develop different decoding algorithms for the SC-SCCs and discuss the associated decoding performance and complexity. Also, several high-level VLSI architectures along with the corresponding synthesis results in a 12 nm process are presented, and various design tradeoffs are provided for these decoding schemes.
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| 8. |
- Mahdavi, Mojtaba, et al.
(författare)
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Spatially Coupled Serially Concatenated Codes: Performance Evaluation and VLSI Design Tradeoffs
- 2022
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Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328. ; 69:5, s. 1962-1975
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Tidskriftsartikel (refereegranskat)abstract
- Spatially coupled serially concatenated codes (SC-SCCs) are constructed by coupling several classical turbo-like component codes. The resulting spatially coupled codes provide a close-to-capacity performance and low error floor,which have attracted a lot of interest in the past few years. The aim of this paper is to perform a comprehensive design space exploration to reveal different aspects of SC-SCCs, which is missing in the literature. More specifically, we investigate the effect of block length, coupling memory, decoding window size, and number of iterations on the decoding performance, complexity, latency, and throughput of SC-SCCs. To this end, we propose two decoding algorithms for the SC-SCCs: block-wise and window-wise decoders. For these, we present VLSI architectural templates and explore them based on building blocks implemented in 12 nm FinFET technology. Linking architectural templates with the new algorithms, we demonstrate various tradeoffs between throughput, silicon area, latency, and decoding performance.
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| 9. |
- Mahdavi, Mojtaba, et al.
(författare)
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The Effect of Coupling Memory and Block Length on Spatially Coupled Serially Concatenated Codes
- 2020
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Ingår i: IEEE 93rd Vehicular Technology Conference (VTC). - 9781728189642 - 9781728189659 ; , s. 1-7
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Konferensbidrag (refereegranskat)abstract
- Spatially coupled serially concatenated codes (SC-SCCs) are a class of spatially coupled turbo-like codes, which have a close-to-capacity performance and low error floor. In this paper, we perform a comprehensive design space exploration, revealing different aspects of SC-SCCs and discussing various design trade-offs. In particular, we investigate the impact of coupling memory, block length, decoding window size, and number of iterations on the performance, complexity, and latency of SC-SCCs. As a result, we propose design guidelines to make the code design independent of the block length. By introducing a modified window decoding schedule, we are able to demonstrate that the block length and coupling memory can be exchanged flexibly without changing the latency and complexity of decoding and without performance loss. Thus, thanks to spatial coupling, a certain code strength and performance can be achieved by either a very small block length or a large one, while the complexity and latency are fixed. Moreover, our results show that using higher coupling memory with smaller blocks can even improve the performance without increasing the latency and complexity. For all considered cases we observe that the performance of SC-SCCs is improved with respect to the uncoupled ensembles for a fixed latency and complexity.
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| 10. |
- Mahdavi, Mojtaba, et al.
(författare)
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Towards Fully Pipelined Decoding of Spatially Coupled Serially Concatenated Codes
- 2021
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Ingår i: IEEE International Symposium on Topics in Coding (ISTC), 2021. - 9781665409438 - 9781665409445 ; , s. 1-5
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Konferensbidrag (refereegranskat)abstract
- Having close-to-capacity performance and low error floor, even for small block lengths, make spatially coupled serially concatenated codes (SC-SCCs) a very promising class of codes. However, classical window decoding of SC-SCCs either limits the minimum block length or requires a large number of iterations, which increases the complexity and constrains the degree to which an SC-SCC decoder architecture can be parallelized. In this paper we propose jumping window decoding (JWD), an algorithmic modification to the scheduling of decoding such that it enables pipelined implementation of SC-SCCs decoder. Also, it provides flexibility in terms of block length and number of iterations and makes them independent of each other. Simulation results show that our scheme outperforms classical window decoding of both SC-SCCs and uncoupled SCCs, in terms of performance. Furthermore, we present a fully pipelined hardware architecture to realize JWD of SC-SCCs along with area estimates in 12nm technology for the respective case study.
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