| 1. |
- Bezati, Endri, et al.
(författare)
-
Clock-gating of streaming applications for energy efficient implementations on FPGAs
- 2016
-
Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - 0278-0070. ; , s. 699-703
-
Tidskriftsartikel (refereegranskat)abstract
- The paper investigates the reduction of dynamic power for streaming applications yielded by asynchronous dataflow designs by using clock gating techniques. Streaming applications constitute a very broad class of computing algorithms in areas such as signal processing, digital media coding, cryptography, video analytics, network routing and packet processing and many others. The paper introduces a set of techniques that, considering the dynamic streaming behavior of algorithms, can achieve power savings by selectively switching off parts of the circuits when they are temporarily inactive. The techniques being independent from the semantic of the application can be applied to any application and can be integrated into the synthesis stage of a high-level dataflow design flow. Experimental results of atsize applications synthesized on FPGAs platforms demonstrate power reductions achievable with no loss in data throughput.
|
|
| 2. |
|
|
| 3. |
- Bezati, Endri, et al.
(författare)
-
High-level Synthesis of Dataflow Programs for Signal Processing Systems
- 2013
-
Konferensbidrag (refereegranskat)abstract
- The growing complexity of signal processing algorithms and platforms poses significant challenges to design methods and implementation tools. High-level dataflow programs, such as those in MPEG's RVC-CAL language, provide abstraction and the opportunity for extensive design-space exploration, but they do raise the problem of efficient automatic synthesis to hardware and software. This paper presents a tool called Xronos that efficiently synthesizes RVC-CAL programs to an RTL-level hardware description and significantly improves on previous efforts in both quality of the resulting implementation and synthesis speed. By directly supporting all the features of the RVC-CAL language, it translates unmodified standard MPEG reference code to a functioning hardware implementation. The paper describes the essential processing architecture of Xronos, the differences from other related approaches and experimental results that show Xronos to produce faster and smaller implementations, while at the same time significantly reducing synthesis times
|
|
| 4. |
- Bezati, Endri, et al.
(författare)
-
High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms
- 2016
-
Ingår i: 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS). - 9781509030774 - 9781509030767 ; , s. 227-234
-
Konferensbidrag (refereegranskat)abstract
- The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on programmable logic devices and embedded processors. Past research has shown that, for complex systems, raising the level of abstraction of design stages does not necessarily come at a penalty in terms of performance or resource requirements. Dataflow programs provide behavioral descriptions capable of expressing both sequential and parallel components of application algorithms and enable natural design abstractions, modularity, and portability. In this paper, an open source tool, implementing dataflow programs onto embedded heterogeneous platforms by means of high-level synthesis, software synthesis and interface synthesis is presented Experimental design results demonstrate the capability and the effectiveness of the tool for implementing a wide range of applications when combined with Vivado HLS.
|
|
| 5. |
- Bezati, Endri, et al.
(författare)
-
High-level system synthesis and optimization of dataflow programs for MPSoCs
- 2017
-
Ingår i: 50th Asilomar Conference on Signals, Systems and Computers, ACSSC 2016. - 9781538639542 ; , s. 417-421
-
Konferensbidrag (refereegranskat)abstract
- The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on reconfigurable and embedded devices. Past research has shown that raising the level of abstraction of design stages does not necessarily gives penalties in terms of performance or resources. Dataflow programs provide behavioral descriptions capable of expressing both sequential and parallel algorithms and enable natural design abstractions, modularity, and portability. In this paper, a tool implementing dataflow programs onto embedded heterogeneous platforms by means of high-level synthesis, software synthesis and interface synthesis is presented for MPSoCs platfroms.
|
|
| 6. |
- Bezati, Endri, et al.
(författare)
-
Synthesis and optimization of high-level stream programs
- 2013
-
Ingår i: Proceedings of the Electronic System Level Synthesis Conference (ESLsyn). - 9781467364140 - 9782953998795
-
Konferensbidrag (refereegranskat)abstract
- In this paper we address the problem of translating high-level stream programs, such as those written in MPEG's RVC-CAL dataflow language, into implementations in programmable hardware. Our focus is on two aspects: sufficient language coverage to make synthesis available for a large class of programs, and methodology and tool support providing analysis and guidance to improve and optimize an initial implementation. Our main results are (1) a synthesis tool that for the first time translates a complete and unmodified MPEG reference implementation into a working hardware description, and (2) a suite of profiling and analysis tools that analyze the structure of computation weighted by data obtained from the synthesis process, and accurately pinpoint parts of the program that are targets for optimization.
|
|
| 7. |
- Bhattacharyya, Shuvra S., et al.
(författare)
-
Overview of the MPEG Reconfigurable Video Coding Framework
- 2011
-
Ingår i: Journal of Signal Processing Systems. - : Springer Science and Business Media LLC. - 1939-8115 .- 1939-8018. ; 63:2, s. 251-263
-
Tidskriftsartikel (refereegranskat)abstract
- Abstract in UndeterminedVideo coding technology in the last 20 yearshas evolved producing a variety of different and com-plex algorithms and coding standards. So far the speci-fication of such standards, and of the algorithms thatbuild them, has been done case by case providingmonolithic textual and reference software specifica-tions in different forms and programming languages.However, very little attention has been given to pro-vide a specification formalism that explicitly presentscommon components between standards, and the incre-mental modifications of such monolithic standards. TheMPEG Reconfigurable Video Coding (RVC) frame-work is a new ISO standard currently under its final stage of standardization, aiming at providing videocodec specifications at the level of library componentsinstead of monolithic algorithms. The new concept is tobe able to specify a decoder of an existing standard ora completely new configuration that may better satisfyapplication-specific constraints by selecting standardcomponents from a library of standard coding algo-rithms. The possibility of dynamic configuration andreconfiguration of codecs also requires new method-ologies and new tools for describing the new bitstreamsyntaxes and the parsers of such new codecs. TheRVC framework is based on the usage of a new actor/dataflow oriented language called Cal for the specifi-cation of the standard library and instantiation of theRVC decoder model. This language has been specifi-cally designed for modeling complex signal processingsystems. Cal dataflow models expose the intrinsic con-currency of the algorithms by employing the notionsof actor programming and dataflow. The paper givesan overview of the concepts and technologies buildingthe standard RVC framework and the non standardtools supporting the RVC model from the instantiationand simulation of the Cal model to software and/orhardware code synthesis.
|
|
| 8. |
- Brunet, Simone Casale, et al.
(författare)
-
Buffer Optimization Based on Critical Path Analysis of a Dataflow Program Design
- 2013
-
Ingår i: IEEE International Symposium on Circuits and Systems.
-
Konferensbidrag (refereegranskat)abstract
- The trade-off between throughput and memory constraints is a common design problem in embedded systems, and especially for streaming applications, where the memory in question usually occurs in the form of buffers for streams of data. This paper presents a methodology, based on the post-processing of dataflow execution traces, that enables designers to make principled choices in the design space for arbitrary streaming applications in a scalable manner. It significantly extends the class of applications over traditional compile-time-only techniques, and effectively enables designers to find a close-to-minimum solution for this NP-complete problem. A heuristic algorithm exploring different buffer size configurations lets designers choose appropriate alternatives and enables them to rapidly navigate the design space. Methodology and experimental results are demonstrated in an at-size scenario using a real-world MPEG-4 SP decoder.
|
|
| 9. |
- Brunet, Simone Casale, et al.
(författare)
-
Design space exploration and implementation of RVC-CAL applications using the TURNUS framework
- 2013
-
Ingår i: 2013 Conference on Design and Architectures for Signal and Image Processing (DASIP). - 1966-7116. - 9791092279023 ; , s. 341-342
-
Konferensbidrag (refereegranskat)abstract
- While research on the design of heterogeneous concurrent systems has a long and rich history, a unified design methodology and tool support has not emerged so far, and thus the creation of such systems remains a difficult, time-consuming and error-prone process. The absence of principled support for system evaluation and optimization at high abstraction levels makes the quality of the resulting implementation highly dependent on the experience or prejudices of the designer. In this work we present TURNUS, a unified dataflow design space exploration framework for heterogeneous parallel systems. It provides high-level modelling and simulation methods and tools for system level performances estimation and optimization. TURNUS represents the outcome of several years of research in the area of co-design exploration for multimedia stream applications. During the presentation, it will be demonstrated how the initial high-level abstraction of the design facilitates the use of different analysis and optimization heuristics. These guide the designer during validation and optimization stages without requiring low-level implementations of parts of the application. Our framework currently yields exploration and optimization results in terms of algorithmic optimization, rapid performance estimation, application throughput, buffer size dimensioning, and power optimization
|
|
| 10. |
- Brunet, Simone Casale, et al.
(författare)
-
Design Space Exploration of High-Level Stream Programs on Parallel Architectures
- 2013
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a dataflow design methodology and an associated co-exploration environment, focusing on the optimization of buffer sizes. The approach is applicable to dynamic dataflow designs and its performance is presented and validated by experimental results on the porting of an MPEG-4 Simple Profile decoder to the STM STHORM manycore platform. For the purpose of this work, the decoder has been written using the RVC-CAL dataflow language standardized by ISO/IEC. Starting from this high-level representation it is demonstrated how the buffer size configuration can be optimized, based on a novel buffer size minimization algorithm suitable for a very general class of dataflow programs.
|
|
