| 1. |
- Bhide, Ameya, et al.
(författare)
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An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS
- 2013
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 60:7, s. 387-391
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents an 8-GS/s 12-bit input ΔΣ digital-to-analog converter (DAC) with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1–1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR, and $-$57-dBc IMD3, with a power consumption of 68 mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.
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| 2. |
- Edman, Anders, et al.
(författare)
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Synchronous Latency-Insensitive Design for Multiple Clock Domain
- 2005
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Ingår i: Proceedings of the IEEE International System-on-Chip Conference (SoCC). - : IEEE Explore. ; , s. 83-86
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Konferensbidrag (refereegranskat)abstract
- Modern system-on-chip designs often require multiple clock frequencies. On the other hand, global interconnects suffer large delays. This paper proposes a method that manages these two problems within the framework of conventional synchronous design flow. The design is partitioned into isochronous blocks already at behavioral level, where each block is synchronous using a local clock. The local clock frequencies are assumed related by rational numbers. Communication between blocks is managed with FIFOs at each receiver, which manage different clock frequencies and hide unknown delays or clock skews. This method guarantees clock true implementation of a clock true behavioral description utilizing a predefined block-to-block latency.
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| 3. |
- Fazli Yeknami, Ali, et al.
(författare)
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A low voltage and process variation tolerant SRAM cell in 90-nm CMOS
- 2010
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Ingår i: International Symposium on VLSI Design Automation and Test. - : IEEE. - 9781424452699 ; , s. 78-81
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Konferensbidrag (refereegranskat)abstract
- In this paper, a new asymmetric 6T (AS6T) SRAM cell is presented in a standard 90-nm CMOS technology employing separate bitline and wordline for read operation. Utilizing separate bitline and wordline during read operation decouples the other cell node from the bitline, hence, enhancing the read static noise margin (SNM) by almost 2 times as compared to the conventional 6T SRAM. The read SNM of 6T and AS6T SRAM cells during a read operation in 1.0 V supply is 85 mV and 159 mV, respectively. The mean μ of the hold SNM for both cells are well above 140 mV, however, the μ of the conventional 6T SRAM is larger than that of AS6T cell. The impact of process parameter variations on read and hold noise margin of the asymmetric 6T cell and the conventional 6T cell, considering various supply voltages, is investigated. The results demonstrate yield improvement, up to 99.5%, and indicate that the supply voltage can scale down to 0.45 V.
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| 4. |
- Fritzin, Jonas, et al.
(författare)
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A Class-D Stage with Harmonic Suppression and DLL-Based Phase Generation
- 2012
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Ingår i: 2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS). - : Lida Ray Technologies Inc.. - 9781467325257 - 9781467325264 ; , s. 45-48
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Konferensbidrag (refereegranskat)abstract
- This paper presents a Class-D stage with 3rd harmonic suppression operating at 2V(DD) (i.e., twice the nominal supply voltage). A DLL-based phase generator is used to generate the phases of the driving signals and by modifying the driver stage 5th harmonic suppression is also possible. The output stage and drivers are based on inverters only, where the short-circuit current is eliminated in the output stage. Operating at 1 GHz, the simulated output power is +19.4 dBm utilizing a 1-V supply and a 5-Omega load, with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 72% and 52%, respectively, including power dissipation in the DLL-based phase generator and drivers. The 3rd harmonic is suppressed 23 dB (-33 dBc) compared to a conventional Class-D stage.
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| 5. |
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| 6. |
- Hansson, Martin, et al.
(författare)
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1.56-GHz On-Chip Resonant Clocking with 2.3X Clock Power-Saving in 130-nm CMOS
- 2006
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Ingår i: Proceedings of the European Solid-State Circuit Conference (ESSCIRC). ; , s. 464-467
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Konferensbidrag (refereegranskat)abstract
- This paper presents a detailed clock jitter characteristic analysis of a fully integrated 1.5-GHz resonant clocking fabricated in 130-nm CMOS, with 57% total clock power saving, compared to the conventional clocking implemented in the same test-chip. The jitter measurement result is in good agreement with the jitter analysis. Furthermore, a jitter-suppression technique based on injection locking phenomenon has been utilized to reduce the clock jitter and to solve the jitter peaking problem. Measurements show about 50% peak-to-peak clock jitter reduction from 28.4 ps to 14.5 ps after the activation of the injection locking.
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| 7. |
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| 8. |
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| 9. |
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| 10. |
- Mesgarzadeh, Behzad, 1977-, et al.
(författare)
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A 2-GHz 7-mW Digital DLL-Based Frequency Multiplier in 90-nm CMOS
- 2008
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Ingår i: ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference. - Bristol, UK : IOP Institute of Physics. - 9781424423620 - 9781424423613 ; , s. 86-89
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Konferensbidrag (refereegranskat)abstract
- This paper presents a low-power low-jitter digital DLL-based frequency multiplier in 90-nm CMOS. In order to reduce the jitter and power consumption due to dithering in the lock condition, digital DLL operates in the open-loop mode after locking. To keep track of any potential phase error introduced by the environmental variations, a compensation mechanism is employed. The proposed frequency multiplier operates at 2-GHz utilizing a 1-V supply. It occupies 0.037 mm2 of active area and dissipates 7-mW power at 2-GHz. The measured peak-to-peak and rms clock jitter at the output of the frequency multiplier are 9.5 ps and 1.6 ps, respectively.
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