| 1. |
- Norell, Håkan
(författare)
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Development, analysis and implementation of pre-processing video filters
- 2006
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The usage of video systems in households and industry has increased rapidly over the past few years. The benefits of visual processing, control and inspection have offered great opportunities for real-time video processing systems (RTVPS) for the general public as well as for heavy industries. The high volume market media systems can absorb a great deal of the cost related to the development of standard components, such as Field Programmable Gate Arrays (FPGAs). The development of industrial systems can benefit from this new technology by utilizing these cheap components. In this thesis, examples of video processing algorithms suitable for pre-processing of digital video applicable for both industrial and media usage will be shown. In addition a methodology supporting the designer in implementing memory architectures suitable for such algorithms is presented. In this thesis two video processing algorithms are presented and described in detail. The common denominator is their utilization of data from temporally adjacent frames in order to be effective, in terms of compression efficiency, and to produce an attractive result for the viewer. However, from the aspect of quality improvement, considerations have to be taken into account in order to enable an actual hardware implementation. Utilizing data from temporally adjacent frames in a real-time data stream is a non-trivial task. From the algorithm designer’s view the data dependencies and memory requirements are not in focus, but for the hardware designer they are. Having the right data available at the right time is the only consideration in order to have a functional system. Present day algorithm and hardware development methods and architectures do not converge into a common design flow, even though this has been attempted. The gap between the algorithm designer and his/her hardware counterpart has to be bridged in order to obtain an efficient and rapid implementation. Methodologies that abstract and reduce the amount of time spent on implementing memory architectures for video processing applications are required. The buffering requirements are often too complex to analyze manually in order to efficiently utilize the resources available in FPGAs. In this thesis a method for the synthesis and implementation of memory architectures for real-time video processing systems, IMapper, is presented. The architecture supports the implementation of spatio- and temporal video processing algorithms and utilizes methodologies for global optimization of on-fabric available memory resources for FPGAs. This methodology provides an efficient and flexible implementation environment and also offers the benefits of the global optimizations it utilizes
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| 2. |
- Imran, Muhammad
(författare)
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Energy Efficient and Programmable Architecture for Wireless Vision Sensor Node
- 2013
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Wireless Vision Sensor Networks (WVSNs) is an emerging field which has attracted a number of potential applications because of smaller per node cost, ease of deployment, scalability and low power stand alone solutions. WVSNs consist of a number of wireless Vision Sensor Nodes (VSNs). VSN has limited resources such as embedded processing platform, power supply, wireless radio and memory. In the presence of these limited resources, a VSN is expected to perform complex vision tasks for a long duration of time without battery replacement/recharging. Currently, reduction of processing and communication energy consumptions have been major challenges for battery operated VSNs. Another challenge is to propose generic solutions for a VSN so as to make these solutions suitable for a number of applications.To meet these challenges, this thesis focuses on energy efficient and programmable VSN architecture for machine vision systems which can classify objects based on binary data. In order to facilitate generic solutions, a taxonomy has been developed together with a complexity model which can be used for systems’ classification and comparison without the need for actual implementation. The proposed VSN architecture is based on tasks partitioning between a VSN and a server as well as tasks partitioning locally on the node between software and hardware platforms. In relation to tasks partitioning, the effect on processing, communication energy consumptions, design complexity and lifetime has been investigated.The investigation shows that the strategy, in which front end tasks up to segmentation, accompanied by a bi-level coding, are implemented on Field Programmable Platform (FPGA) with small sleep power, offers a generalized low complexity and energy efficient VSN architecture. The implementation of data intensive front end tasks on hardware reconfigurable platform reduces processing energy. However, there is a scope for reducing communication energy, related to output data. This thesis also explores data reduction techniques including image coding, region of interest coding and change coding which reduces output data significantly.For proof of concept, VSN architecture together with tasks partitioning, bi-level video coding, duty cycling and low complexity background subtraction technique has been implemented on real hardware and functionality has been verified for four applications including particle detection system, remote meter reading, bird detection and people counting. The results based on measured energy values shows that, depending on the application, the energy consumption can be reduced by a factor of approximately 1.5 up to 376 as compared to currently published VSNs. The lifetime based on measured energy values showed that for a sample period of 5 minutes, VSN can achieve 3.2 years lifetime with a battery of 37.44 kJ energy. In addition to this, proposed VSN offers generic architecture with smaller design complexity on hardware reconfigurable platform and offers easy adaptation for a number of applications as compared to published systems.
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| 3. |
- Thörnberg, Benny
(författare)
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Memory modeling and synthesis for real-time video processing systems
- 2006
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- In this thesis, a new design methodology and new tools for modeling and synthesis of real-time video processing systems are presented. A real-time video processing system is a system that performs computations on a continuous sequence of images. Image processing is a memory intensive application. This, in turn, leads to the design challenge of bridging the classical gap of speed between memories and computational units. Several techniques exist for building memory hierarchies that exploit data- locality and reuse in order to overcome this memory gap. However, the support from tools to aid the designer in dataflow analysis and memory design is very modest. Additional constructs for modeling electronic systems enable well-known sequential programming languages such as C/C++ to be used for system modeling. Ocapi and SystemC, two object-oriented specification methods are compared in a case study. In this study, SystemC is found to be the most suitable specification method for video processing systems. Most operations invoked in video processing are neighborhood oriented. For a video system designer, this spatio-temporal collection of pixels represents a natural abstraction. In addition, the same pixel neighborhood reflects data dependencies that are crucial to system synthesis. An extended SystemC modeling methodology, called IMEM is presented. IMEM can be used to capture memory transactions and stream interfaces based on the pixel neighborhood as an abstraction. Two important steps towards synthesis of video systems onto Field Programmable Gate Arrays (FPGAs) are presented. These two steps are parts of a decomposition of the complete synthesis task. Firstly, the optimal sizes and placements of all FIFO-buffers in the memory system are optimized. Bit-widths, pipelining and possible sharing of FIFO-buffers among several data flow dependencies are considered at this step. Secondly, the set of FIFO-buffers are allocated onto a set of dual-ported fined grained memories. Both synthesis steps are formally modeled using network flow techniques and linear programming. In addition, a synthesis method that can automatically transform an IMEM model of a single spatial neighborhood into a multimedia processor implementation is presented. The cache and the instruction scheduler performance are both optimized by the tool. IMEM is an application specific methodology that provides the nonhardware skilled video designer with an easy programming model and an FPGA synthesis tool. Memory usage is modeled separately from computation. This is a key feature since memory usage is accepted as being the biggest design bottleneck for video processing.
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