| 1. |
- Andric, Stefan, et al.
(författare)
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Design of III-V Vertical Nanowire MOSFETs for Near-Unilateral Millimeter-Wave Operation
- 2021
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Ingår i: EuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference. - 9782874870606 ; , s. 85-88
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Konferensbidrag (refereegranskat)abstract
- Vertical nanowire MOSFETs exhibit asymmetric gate capacitances, allowing for their independent engineering to improve device high frequency performance. Minimizing gate-drain parasitic capacitance with the use of a vertical sidewall spacer enables universal feedback neutralization and a unilateral circuit design. For vertical spacer thickness above 20 nm, the gate-drain capacitance variability is reduced. Device technology is verified by simulation of 60 GHz three-stage low-noise amplifier. The amplifier exhibits 10 dB gain and 6.9 dB noise figure. The noise figure can be further reduced to 5.9 dB by combining several feedback techniques. The use of capacitance minimization reduces circuit sensitivity to device variation, demonstrating the potential of this technology in implementation of mm-wave communication and sensing systems.
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| 2. |
- Andric, Stefan, et al.
(författare)
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Lateral III-V Nanowire MOSFETs in Low-Noise Amplifier Stages
- 2022
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Ingår i: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480. ; 70:2, s. 1284-1291
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Tidskriftsartikel (refereegranskat)abstract
- Lateral III-V nanowire (NW) MOSFETs are a promising candidate for high-frequency electronics. However, their circuit performance is not yet assessed. Here, we integrate lateral nanowires (LNWs) in a circuit environment and characterize the transistors and amplifiers. MOSFETs are fabricated in a simple scheme with a dc transconductance of up to 1.3 mS/μm, ON-resistance down to 265 Ω · μ m, and cutoff frequencies up to 250 GHz, measured on the circuit level. The circuit model estimates 25% device parasitic capacitance increase due to back-end-of-line (BEOL) dielectric cladding. A low-noise amplifier input stage is designed with optimum network design for a noise matched input and an inductive peaking output. The input stage shows up to 4-dB gain and 2.5-dB noise figure (NF), at 60 GHz. Utilizing gate-length scaling in the circuit environment, the obtained normalized intrinsic gate capacitance value of 0.34-aF/nm gate length, per NW, corresponds well to the predicted theoretical value, demonstrating the circuit's ability to provide intrinsic device parameters. This is the first mm-wave validation of noise models for III-V LNW MOSFETs. The results demonstrate the potential for utilization of the technology platform for low-noise applications.
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| 3. |
- Andric, Stefan, et al.
(författare)
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Low-temperature back-end-of-line technology compatible with III-V nanowire MOSFETs
- 2019
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Ingår i: Journal of Vacuum Science and Technology B: Nanotechnology and Microelectronics. - : American Vacuum Society. - 2166-2746 .- 2166-2754. ; 37:6
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Tidskriftsartikel (refereegranskat)abstract
- We present a low-temperature processing scheme for the integration of either lateral or vertical nanowire (NW) transistors with a multilayer back-end-of-line interconnect stack. The nanowire device temperature budget has been addressed, and materials for the interconnect fabrication have been selected accordingly. A benzocyclobutene (BCB) polymer is used as an interlayer dielectric, with interconnect vias formed by reactive ion etching. A study on via etching conditions for multiple interlayer dielectric thicknesses reveals that the sidewall slope can be engineered. An optimal reactive ion etch is identified at 250 mTorr chamber pressure and power of 160 W, using an SF6 to O2 gas mix of 4%. This results in a low via resistance, even for scaled structures. The BCB dielectric etch rate and dielectric-to-soft mask etch selectivity are quantified. Electrical measurements on lateral and vertical III-V NW transistors, before and after the back-end-of-line process, are presented. No performance degradation is observed, only minor differences that are attributed to contact annealing and threshold voltage shift.
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| 4. |
- Andric, Stefan, et al.
(författare)
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Millimeter-Wave Vertical III-V Nanowire MOSFET Device-To-Circuit Co-Design
- 2021
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Ingår i: IEEE Transactions on Nanotechnology. - 1536-125X. ; 20, s. 434-440
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Tidskriftsartikel (refereegranskat)abstract
- Vertical III-V nanowire MOSFETs show potential towards the ultimate transistor scaling. A high transconductance and current density are achieved based on the gate-all-around architecture. This work presents a high-frequency design of such devices, achieving more than 600 GHz cut-off frequencies (fT, fmax), at 20 nm gate length. Furthermore, capacitance design and scaling trends, supported by COMSOL Multiphysics simulations derive state-of-the-art parasitics magnitudes for vertical devices in general, reaching gate-drain capacitance values of 17 aF/wire, corresponding to 0.2 fF/m. A unique co-designed feedback resonant circuit makes the device unilateral, exhibiting up to 15 dB gain in D-band at 0.5 V supply, and with a current density of 0.5 mA/m. Finally, a 2-stage low noise amplifier is designed using an optimum matching concept to utilize the full available bandwidth. The resulting circuit performance is independent of transistor gate length, since any decrease in device intrinsic capacitance is assisted by an increase in device overlap capacitances in a setting unique to a current implementation of vertical nanowire MOSFETs. With this approach, amplifiers are designed with more than 20 dB gain and minimum noise figure of 2.5 dB in a simulation environment at 140 GHz. The proposed technology and design platform show a great potential in future low-power communication systems.
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| 5. |
- Fhager, Lars Ohlsson, et al.
(författare)
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Pulsed Millimeter Wave Radar for Hand Gesture Sensing and Classification
- 2019
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Ingår i: IEEE Sensors Letters. - 2475-1472. ; 3:12
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Tidskriftsartikel (refereegranskat)abstract
- A pulsed millimeter wave radar operating at a frame rate of 144 Hz is utilized to record 2160 scattering signatures of 12 generic hand gestures. Gesture recognition is achieved by machine learning, utilizing transfer learning on a pretrained convolutional neural network. This yields excellent classification results with a validation accuracy of 99.5%, based on a 60% training versus 40% validation split. The corresponding confusion matrix is also presented, showing a high level of classification orthogonality between the tested gestures. This is the first demonstration where data from a pulsed millimeter wave radar is used for gesture recognition by machine learning. It proves that the range-time envelope representation of high frame-rate data from a pulsed radar is suitable for hand gesture recognition. Further improvements are expected for more complex detection schemes and tailored neural networks.
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| 6. |
- Heunisch, Sebastian, et al.
(författare)
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A phase-correlated duo-binary waveform generation technique for millimeter-wave radar pulses
- 2020
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Ingår i: International Journal of Circuit Theory and Applications. - : Wiley. - 0098-9886 .- 1097-007X. ; 48:1, s. 103-114
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Tidskriftsartikel (refereegranskat)abstract
- We propose a technique for generating millimeter-wave radar waveforms using edge-triggered pulse generator circuits. By synchronizing the chip rate to the oscillation frequency of a binary control signal, a phase shift is introduced in the generated pulses. This way, the millimeter-wave signal can be phase-modulated without the need of additional circuit elements. We show that high-resolution radar waveforms with low range side lobes can be generated with this technique. Using brute-force optimization, we evaluate all possible sequences up to a sequence length of 25 chips and identify optimal waveforms for each length. Optimal sequences with the energy centered at zero delay and side lobes not exceeding unity are presented. The optimized waveforms are measured and verified using an in-house resonant tunneling diode (RTD) metal-oxide-semiconductor field-effect transistor (MOSFET) pulse generator. The matched filter response of the optimal waveforms is reproduced closely in the measurements. The results enable increased sensitivity in radar systems using coherent millimeter-wave pulse generators for low power applications, as for instance, radar gesture recognition in handheld devices. Using pulsed millimeter-wave radar systems with low duty cycles, continuously running oscillators can be avoided and systems with ultra-low power consumption are possible.
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| 7. |
- Heunisch, Sebastian, et al.
(författare)
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Millimeter-Wave Pulse Radar Scattering Measurements on the Human Hand
- 2019
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Ingår i: IEEE Antennas and Wireless Propagation Letters. - 1536-1225. ; 18:7, s. 1377-1380
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Tidskriftsartikel (refereegranskat)abstract
- We investigate the backscattering of low-power millimeter-wave pulses (wavelets) on the human hand in order to determine the detection limit of scattering features. Using an in-house wavelet radar setup with a nominal spatial resolution of 2.29 cm, we measure a hand in three different postures: a flat hand, a fist, and a hand with raised index finger. For the latter, we are able to resolve backscattering from at least two different scattering centers, attributed to the heel of the hand and the finger. The effective radar cross section in the measurements was in the range from -29.5 to -35.1 dBsm. We demonstrate that detecting scattering features from the hand with an equivalent isotropically radiated power spectral density of -68.5 dBm/MHz is possible. This shows that, compared to most conventional radar systems operating close to the regulatory emission limits (13 dBm/MHz), the energy of the transmitted waveform can be significantly reduced. The result shows that low-power radar systems for gesture recognition are feasible using pulsed systems with ultrashort pulses and low duty cycles. This is key for integration in battery-powered devices.
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| 8. |
- Rangasamy, Gautham, et al.
(författare)
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gm/Id Analysis of vertical nanowire III–V TFETs
- 2023
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Ingår i: Electronics Letters. - 1350-911X. ; 59:18
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Tidskriftsartikel (refereegranskat)abstract
- Experimental data on analog performance of gate-all-around III-V vertical Tunnel Field-Effect Transistors (TFETs) and circuits are presented. The individual device shows a minimal subthreshold swing of 44 mV/dec and transconductance efficiency of 50 V−1 for current range of 9 nA/μm to 100 nA/μm and at a drain voltage of 100 mV. This TFET demonstrates translinearity between transconductance and drain current for over a decade of current, paving way for low power current-mode analog IC design. To explore this design principle, a current conveyor circuit is implemented, which exhibits large-signal voltage gain of 0.89 mV/mV, current gain of 1nA/nA and an operating frequency of 320 kHz. Furthermore, at higher drain bias of 500 mV, the device shows maximum transconductance of 72 μS/μm and maximum drain current of 26 μA/μm. The device, thereby, can be operated as a current mode device at lower bias voltage and as voltage mode device at higher bias voltage.
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| 9. |
- Rangasamy, Gautham, et al.
(författare)
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Self-Heating in Gate-All-Around Vertical III-V InAs/InGaAs MOSFETs
- 2023
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Ingår i: IEEE Electron Device Letters. - 0741-3106. ; 44:7, s. 1212-1215
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Tidskriftsartikel (refereegranskat)abstract
- We investigate self-heating in vertical, gate-all-around III-V InAs/InGaAs nanowire MOSFETs using pulsed IV measurements at various temperatures. Low temperature measurements reveal a negative output conductance indicating self-heating in the transistor. Under pulsed measurements, an increase in drain current (15%) and transconductance (30%) are observed at room temperature, with values influenced by the pulse width. This effect on performance is quantified with determination of the thermal resistance and capacitance. Furthermore, a first order thermal circuit is modelled based on the thermal impedances. The results indicate that the intrinsic temperature rises to 385 K when the device is operated in DC at room temperature (300 K) with a thermal time constant of 1~μ s. We find that self-heating is a limiting factor for device performance.
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| 10. |
- Rangasamy, Gautham, et al.
(författare)
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TFET Circuit Configurations Operating below 60 mV/dec
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Ingår i: IEEE Transactions on Nanotechnology. - 1536-125X. ; , s. 1-8
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Tidskriftsartikel (refereegranskat)abstract
- Tunnel Field-Effect Transistors (TFETs) offer more energy efficient alternative to CMOS for design of low power circuits. In spite of this potential, circuits based on TFETs have not been experimentally demonstrated so far. In this letter, we explore TFET fabrication and basic functionality of n-TFET based circuits in the following configurations: a current mirror, a diode-connected inverter, and a cascode. Individual TFETs in the circuit operate well below 60 mV/dec operation with minimum achieved subthreshold swing (SS) of 30 mV/dec at drain voltage of 400 mV. To analyse the circuit operation, individual devices are connected via FEOL and are biased at 300 mV supply voltage, with an input frequency of 200 kHz. The measured circuit configurations demonstrate the expected functionality.
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