| 1. |
- Andric, Stefan, et al.
(author)
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Design of III-V Vertical Nanowire MOSFETs for Near-Unilateral Millimeter-Wave Operation
- 2021
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In: EuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference. - 9782874870606 ; , s. 85-88
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Conference paper (peer-reviewed)abstract
- Vertical nanowire MOSFETs exhibit asymmetric gate capacitances, allowing for their independent engineering to improve device high frequency performance. Minimizing gate-drain parasitic capacitance with the use of a vertical sidewall spacer enables universal feedback neutralization and a unilateral circuit design. For vertical spacer thickness above 20 nm, the gate-drain capacitance variability is reduced. Device technology is verified by simulation of 60 GHz three-stage low-noise amplifier. The amplifier exhibits 10 dB gain and 6.9 dB noise figure. The noise figure can be further reduced to 5.9 dB by combining several feedback techniques. The use of capacitance minimization reduces circuit sensitivity to device variation, demonstrating the potential of this technology in implementation of mm-wave communication and sensing systems.
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| 2. |
- Andric, Stefan, et al.
(author)
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Lateral III-V Nanowire MOSFETs in Low-Noise Amplifier Stages
- 2022
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In: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480. ; 70:2, s. 1284-1291
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Journal article (peer-reviewed)abstract
- Lateral III-V nanowire (NW) MOSFETs are a promising candidate for high-frequency electronics. However, their circuit performance is not yet assessed. Here, we integrate lateral nanowires (LNWs) in a circuit environment and characterize the transistors and amplifiers. MOSFETs are fabricated in a simple scheme with a dc transconductance of up to 1.3 mS/μm, ON-resistance down to 265 Ω · μ m, and cutoff frequencies up to 250 GHz, measured on the circuit level. The circuit model estimates 25% device parasitic capacitance increase due to back-end-of-line (BEOL) dielectric cladding. A low-noise amplifier input stage is designed with optimum network design for a noise matched input and an inductive peaking output. The input stage shows up to 4-dB gain and 2.5-dB noise figure (NF), at 60 GHz. Utilizing gate-length scaling in the circuit environment, the obtained normalized intrinsic gate capacitance value of 0.34-aF/nm gate length, per NW, corresponds well to the predicted theoretical value, demonstrating the circuit's ability to provide intrinsic device parameters. This is the first mm-wave validation of noise models for III-V LNW MOSFETs. The results demonstrate the potential for utilization of the technology platform for low-noise applications.
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| 3. |
- Andric, Stefan, et al.
(author)
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Low-temperature back-end-of-line technology compatible with III-V nanowire MOSFETs
- 2019
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In: Journal of Vacuum Science and Technology B: Nanotechnology and Microelectronics. - : American Vacuum Society. - 2166-2746 .- 2166-2754. ; 37:6
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Journal article (peer-reviewed)abstract
- We present a low-temperature processing scheme for the integration of either lateral or vertical nanowire (NW) transistors with a multilayer back-end-of-line interconnect stack. The nanowire device temperature budget has been addressed, and materials for the interconnect fabrication have been selected accordingly. A benzocyclobutene (BCB) polymer is used as an interlayer dielectric, with interconnect vias formed by reactive ion etching. A study on via etching conditions for multiple interlayer dielectric thicknesses reveals that the sidewall slope can be engineered. An optimal reactive ion etch is identified at 250 mTorr chamber pressure and power of 160 W, using an SF6 to O2 gas mix of 4%. This results in a low via resistance, even for scaled structures. The BCB dielectric etch rate and dielectric-to-soft mask etch selectivity are quantified. Electrical measurements on lateral and vertical III-V NW transistors, before and after the back-end-of-line process, are presented. No performance degradation is observed, only minor differences that are attributed to contact annealing and threshold voltage shift.
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| 4. |
- Andric, Stefan, et al.
(author)
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Low-Temperature Front-Side BEOL Technology with Circuit Level Multiline Thru-Reflect-Line Kit for III-V MOSFETs on Silicon
- 2019
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In: 2019 92nd ARFTG Microwave Measurement Conference : Next Generation Microwave and Millimeter-Wave Measurement Techniques and Systems, ARFTG 2019 - Next Generation Microwave and Millimeter-Wave Measurement Techniques and Systems, ARFTG 2019. - 9781538665992
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Conference paper (peer-reviewed)abstract
- A multiline Thru-Reflect-Line (mTRL) calibration and parasitic pad removal kit is presented, intended for mm-wave III-V nanowire MOSFET characterization. Multiline TRL is implemented in a low-temperature BEOL process with substrate decoupled microstrip transmission lines. The transmission line characteristic impedance needed for accurate mTRL calibration is modelled. Simulated transmission line parameters show a good fit with measured transmission line data, including line characteristic impedance variation. Line loss less than 0.5 dB/mm up to 50 GHz is obtained. Finally, interconnect via section is calibrated and modelled, showing mTRL's ability to obtain small parasitic parameters.
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| 5. |
- Andric, Stefan, et al.
(author)
-
Millimeter-Wave Vertical III-V Nanowire MOSFET Device-To-Circuit Co-Design
- 2021
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In: IEEE Transactions on Nanotechnology. - 1536-125X. ; 20, s. 434-440
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Journal article (peer-reviewed)abstract
- Vertical III-V nanowire MOSFETs show potential towards the ultimate transistor scaling. A high transconductance and current density are achieved based on the gate-all-around architecture. This work presents a high-frequency design of such devices, achieving more than 600 GHz cut-off frequencies (fT, fmax), at 20 nm gate length. Furthermore, capacitance design and scaling trends, supported by COMSOL Multiphysics simulations derive state-of-the-art parasitics magnitudes for vertical devices in general, reaching gate-drain capacitance values of 17 aF/wire, corresponding to 0.2 fF/m. A unique co-designed feedback resonant circuit makes the device unilateral, exhibiting up to 15 dB gain in D-band at 0.5 V supply, and with a current density of 0.5 mA/m. Finally, a 2-stage low noise amplifier is designed using an optimum matching concept to utilize the full available bandwidth. The resulting circuit performance is independent of transistor gate length, since any decrease in device intrinsic capacitance is assisted by an increase in device overlap capacitances in a setting unique to a current implementation of vertical nanowire MOSFETs. With this approach, amplifiers are designed with more than 20 dB gain and minimum noise figure of 2.5 dB in a simulation environment at 140 GHz. The proposed technology and design platform show a great potential in future low-power communication systems.
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| 6. |
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| 7. |
- Egard, Mikael, et al.
(author)
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Frequency Modulation in mm-Wave InGaAs MOSFET/RTD Wavelet Generators
- 2013
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In: 2013 International Conference on Indium Phosphide and Related Materials (IPRM). - 1092-8669. ; , s. 1-2
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Conference paper (peer-reviewed)abstract
- Co-integration of an InGaAs MOSFET and an RTD is performed to realize a wavelet generator. The large transconductance of the MOSFET (1.9 mS/mu m) is used to switch the current in an oscillator circuit and coherent wavelets down to 41 ps are generated in the frequency domain of 50 to 100 GHz. The lowest power consumption measured is 1.9 pJ/pulse. It is found that the supply bias can be used to modulate the center frequency of the wavelets.
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| 8. |
- Egard, Mikael, et al.
(author)
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High-Frequency Performance of Self-Aligned Gate-Last Surface Channel In0.53Ga0.47As MOSFET
- 2012
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In: IEEE Electron Device Letters. - 0741-3106. ; 33:3, s. 369-371
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Journal article (peer-reviewed)abstract
- We have developed a self-aligned L-g = 55 nm In-0.53 Ga-0.47 As MOSFET incorporating metal-organic chemical vapor deposition regrown n(++) In0.6Ga0.4As source and drain regions, which enables a record low on-resistance of 199 Omega mu m. The regrowth process includes an InP support layer, which is later removed selectively to the n(++) contact layer. This process forms a high-frequency compatible device using a low-complexity fabrication scheme. We report on high-frequency measurements showing f(max) of 292 GHz and f(t) of 244 GHz. These results are accompanied by modeling of the device, which accounts for the frequency response of gate oxide border traps and impact ionization phenomenon found in narrow band gap FETs. The device also shows a high drive current of 2.0 mA/mu m and a high extrinsic transconductance of 1.9 mS/mu m. These excellent properties are attributed to the use of a gate-last process, which does not include high temperature or dry-etch processes.
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| 9. |
- Egard, Mikael, et al.
(author)
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High Transconductance Self-Aligned Gate-Last Surface Channel In0.53Ga0.47As MOSFET
- 2011
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In: 2011 IEEE International Electron Devices Meeting (IEDM). - 9781457705052
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Conference paper (peer-reviewed)abstract
- In this paper we present a 55 nm gate length In0.53Ga0.47As MOSFET with extrinsic transconductance of 1.9 mS/mu m and on-resistance of 199 Omega mu m. T he self-aligned MOSFET is formed using metalorganic chemical vapor deposition regrowth of highly doped source and drain access regions. The fabricated 140 nm gate length devices shows a low subthreshold swing of 79 mV/decade, which is attributed to the described low temperature gate-last process scheme.
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| 10. |
- Egard, Mikael, et al.
(author)
-
In0.53Ga0.47As RTD-MOSFET Millimeter-Wave Wavelet Generator
- 2012
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In: IEEE Electron Device Letters. - 0741-3106. ; 33:7, s. 970-972
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Journal article (peer-reviewed)abstract
- We report on the fabrication of a self-aligned regrown In0.53Ga0.47As metal-oxide-semiconductor field-effect transistor (MOSFET) and a resonant tunneling diode (RTD). The performance of these devices is demonstrated by integrating them in parallel with an inductive coplanar waveguide stub to form a highly energy-efficient 70-GHz wavelet generator. The fast switching and low on-resistance of the MOSFET make it possible to kick-start and rapidly quench this RTD-driven oscillator circuit, which produces 41-ps-short wavelets at 15 Gpulses/s, a peak output power of 7 dBm, and an energy consumption of 1.9 pJ/pulse.
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